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Benjamin Linnbd168
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wifi: mt76: mt7996: add DMA support for mt7992
Add DMA TX/RX queues and RRO init flow for mt7992 chipsets. This is a preliminary patch for mt7992 chipsets support. Co-developed-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com> Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com> Co-developed-by: Shayne Chen <shayne.chen@mediatek.com> Signed-off-by: Shayne Chen <shayne.chen@mediatek.com> Signed-off-by: Benjamin Lin <benjamin-jw.lin@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
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-17
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4 files changed

+61
-17
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drivers/net/wireless/mediatek/mt76/mt7996/dma.c

Lines changed: 47 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -57,13 +57,19 @@ static void mt7996_dma_config(struct mt7996_dev *dev)
5757
RXQ_CONFIG(MT_RXQ_MCU, WFDMA0, MT_INT_RX_DONE_WM, MT7996_RXQ_MCU_WM);
5858
RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, MT7996_RXQ_MCU_WA);
5959

60-
/* band0/band1 */
60+
/* mt7996: band0 and band1, mt7992: band0 */
6161
RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0, MT7996_RXQ_BAND0);
6262
RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN, MT7996_RXQ_MCU_WA_MAIN);
6363

64-
/* band2 */
65-
RXQ_CONFIG(MT_RXQ_BAND2, WFDMA0, MT_INT_RX_DONE_BAND2, MT7996_RXQ_BAND2);
66-
RXQ_CONFIG(MT_RXQ_BAND2_WA, WFDMA0, MT_INT_RX_DONE_WA_TRI, MT7996_RXQ_MCU_WA_TRI);
64+
if (is_mt7996(&dev->mt76)) {
65+
/* mt7996 band2 */
66+
RXQ_CONFIG(MT_RXQ_BAND2, WFDMA0, MT_INT_RX_DONE_BAND2, MT7996_RXQ_BAND2);
67+
RXQ_CONFIG(MT_RXQ_BAND2_WA, WFDMA0, MT_INT_RX_DONE_WA_TRI, MT7996_RXQ_MCU_WA_TRI);
68+
} else {
69+
/* mt7992 band1 */
70+
RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1, MT7996_RXQ_BAND1);
71+
RXQ_CONFIG(MT_RXQ_BAND1_WA, WFDMA0, MT_INT_RX_DONE_WA_EXT, MT7996_RXQ_MCU_WA_EXT);
72+
}
6773

6874
if (dev->has_rro) {
6975
/* band0 */
@@ -90,8 +96,12 @@ static void mt7996_dma_config(struct mt7996_dev *dev)
9096

9197
/* data tx queue */
9298
TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0);
93-
TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1);
94-
TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND2, MT7996_TXQ_BAND2);
99+
if (is_mt7996(&dev->mt76)) {
100+
TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1);
101+
TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND2, MT7996_TXQ_BAND2);
102+
} else {
103+
TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1);
104+
}
95105

96106
/* mcu tx queue */
97107
MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, MT7996_TXQ_MCU_WM);
@@ -111,6 +121,7 @@ static u32 __mt7996_dma_prefetch_base(u16 *base, u8 depth)
111121
static void __mt7996_dma_prefetch(struct mt7996_dev *dev, u32 ofs)
112122
{
113123
u16 base = 0;
124+
u8 queue;
114125

115126
#define PREFETCH(_depth) (__mt7996_dma_prefetch_base(&base, (_depth)))
116127
/* prefetch SRAM wrapping boundary for tx/rx ring. */
@@ -123,9 +134,14 @@ static void __mt7996_dma_prefetch(struct mt7996_dev *dev, u32 ofs)
123134
mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(0x2));
124135
mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(0x2));
125136
mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN_WA) + ofs, PREFETCH(0x2));
126-
mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2_WA) + ofs, PREFETCH(0x2));
137+
138+
queue = is_mt7996(&dev->mt76) ? MT_RXQ_BAND2_WA : MT_RXQ_BAND1_WA;
139+
mt76_wr(dev, MT_RXQ_BAND1_CTRL(queue) + ofs, PREFETCH(0x2));
140+
127141
mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x10));
128-
mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2) + ofs, PREFETCH(0x10));
142+
143+
queue = is_mt7996(&dev->mt76) ? MT_RXQ_BAND2 : MT_RXQ_BAND1;
144+
mt76_wr(dev, MT_RXQ_BAND1_CTRL(queue) + ofs, PREFETCH(0x10));
129145

130146
if (dev->has_rro) {
131147
mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_RRO_BAND0) + ofs,
@@ -488,7 +504,7 @@ int mt7996_dma_init(struct mt7996_dev *dev)
488504
if (ret)
489505
return ret;
490506

491-
/* rx data queue for band0 and band1 */
507+
/* rx data queue for band0 and mt7996 band1 */
492508
if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) {
493509
dev->mt76.q_rx[MT_RXQ_MAIN].flags = MT_WED_Q_RX(0);
494510
dev->mt76.q_rx[MT_RXQ_MAIN].wed = wed;
@@ -517,7 +533,7 @@ int mt7996_dma_init(struct mt7996_dev *dev)
517533
return ret;
518534

519535
if (mt7996_band_valid(dev, MT_BAND2)) {
520-
/* rx data queue for band2 */
536+
/* rx data queue for mt7996 band2 */
521537
rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND2) + hif1_ofs;
522538
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2],
523539
MT_RXQ_ID(MT_RXQ_BAND2),
@@ -527,7 +543,7 @@ int mt7996_dma_init(struct mt7996_dev *dev)
527543
if (ret)
528544
return ret;
529545

530-
/* tx free notify event from WA for band2
546+
/* tx free notify event from WA for mt7996 band2
531547
* use pcie0's rx ring3, but, redirect pcie0 rx ring3 interrupt to pcie1
532548
*/
533549
if (mtk_wed_device_active(wed_hif2) && !dev->has_rro) {
@@ -542,6 +558,26 @@ int mt7996_dma_init(struct mt7996_dev *dev)
542558
MT_RXQ_RING_BASE(MT_RXQ_BAND2_WA));
543559
if (ret)
544560
return ret;
561+
} else if (mt7996_band_valid(dev, MT_BAND1)) {
562+
/* rx data queue for mt7992 band1 */
563+
rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1) + hif1_ofs;
564+
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1],
565+
MT_RXQ_ID(MT_RXQ_BAND1),
566+
MT7996_RX_RING_SIZE,
567+
MT_RX_BUF_SIZE,
568+
rx_base);
569+
if (ret)
570+
return ret;
571+
572+
/* tx free notify event from WA for mt7992 band1 */
573+
rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1_WA) + hif1_ofs;
574+
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1_WA],
575+
MT_RXQ_ID(MT_RXQ_BAND1_WA),
576+
MT7996_RX_MCU_RING_SIZE,
577+
MT_RX_BUF_SIZE,
578+
rx_base);
579+
if (ret)
580+
return ret;
545581
}
546582

547583
if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed) &&

drivers/net/wireless/mediatek/mt76/mt7996/init.c

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -513,7 +513,12 @@ void mt7996_mac_init(struct mt7996_dev *dev)
513513
mt76_rmw_field(dev, MT_DMA_TCRF1(2), MT_DMA_TCRF1_QIDX, 0);
514514

515515
/* rro module init */
516-
mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2);
516+
if (is_mt7996(&dev->mt76))
517+
mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2);
518+
else
519+
mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE,
520+
dev->hif2 ? 7 : 0);
521+
517522
if (dev->has_rro) {
518523
u16 timeout;
519524

@@ -570,7 +575,7 @@ static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy,
570575
if (phy)
571576
return 0;
572577

573-
if (band == MT_BAND2 && dev->hif2) {
578+
if (is_mt7996(&dev->mt76) && band == MT_BAND2 && dev->hif2) {
574579
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
575580
wed = &dev->mt76.mmio.wed_hif2;
576581
}

drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -104,10 +104,10 @@ enum mt7996_rxq_id {
104104
MT7996_RXQ_MCU_WM = 0,
105105
MT7996_RXQ_MCU_WA,
106106
MT7996_RXQ_MCU_WA_MAIN = 2,
107-
MT7996_RXQ_MCU_WA_EXT = 2,/* unused */
107+
MT7996_RXQ_MCU_WA_EXT = 3, /* for mt7992 */
108108
MT7996_RXQ_MCU_WA_TRI = 3,
109109
MT7996_RXQ_BAND0 = 4,
110-
MT7996_RXQ_BAND1 = 4,/* unused */
110+
MT7996_RXQ_BAND1 = 5, /* for mt7992 */
111111
MT7996_RXQ_BAND2 = 5,
112112
MT7996_RXQ_RRO_BAND0 = 8,
113113
MT7996_RXQ_RRO_BAND1 = 8,/* unused */
@@ -399,6 +399,9 @@ mt7996_phy3(struct mt7996_dev *dev)
399399
static inline bool
400400
mt7996_band_valid(struct mt7996_dev *dev, u8 band)
401401
{
402+
if (is_mt7992(&dev->mt76))
403+
return band <= MT_BAND1;
404+
402405
/* tri-band support */
403406
if (band <= MT_BAND2 &&
404407
mt76_get_field(dev, MT_PAD_GPIO, MT_PAD_GPIO_ADIE_COMB) <= 1)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -461,12 +461,12 @@ enum base_rev {
461461
#define MT_INT1_MASK_CSR MT_WFDMA0_PCIE1(0x204)
462462

463463
#define MT_INT_RX_DONE_BAND0 BIT(12)
464-
#define MT_INT_RX_DONE_BAND1 BIT(12)
464+
#define MT_INT_RX_DONE_BAND1 BIT(13) /* for mt7992 */
465465
#define MT_INT_RX_DONE_BAND2 BIT(13)
466466
#define MT_INT_RX_DONE_WM BIT(0)
467467
#define MT_INT_RX_DONE_WA BIT(1)
468468
#define MT_INT_RX_DONE_WA_MAIN BIT(2)
469-
#define MT_INT_RX_DONE_WA_EXT BIT(2)
469+
#define MT_INT_RX_DONE_WA_EXT BIT(3) /* for mt7992 */
470470
#define MT_INT_RX_DONE_WA_TRI BIT(3)
471471
#define MT_INT_RX_TXFREE_MAIN BIT(17)
472472
#define MT_INT_RX_TXFREE_TRI BIT(15)

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