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SruChallaherbertx
SruChalla
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herbertx
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crypto: octeontx2 - hardware configuration for inline IPsec
On OcteonTX2/OctoenTX3 variants of silicon, Admin function (AF) handles resource allocation and configuration for PFs and their VFs. PFs request the AF directly, via mailboxes. Unlike PFs, VFs cannot send a mailbox request directly. A VF sends mailbox messages to its parent PF, with which it shares a mailbox region. The PF then forwards these messages to the AF. This patch adds code to configure inline-IPsec HW resources for CPT VFs as CPT VFs cannot send a mailbox request directly to AF. Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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10 files changed

+261
-38
lines changed

10 files changed

+261
-38
lines changed

‎drivers/crypto/marvell/octeontx2/otx2_cpt_common.h‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,10 +40,25 @@ enum otx2_cpt_eng_type {
4040
};
4141

4242
/* Take mbox id from end of CPT mbox range in AF (range 0xA00 - 0xBFF) */
43+
#define MBOX_MSG_RX_INLINE_IPSEC_LF_CFG 0xBFE
4344
#define MBOX_MSG_GET_ENG_GRP_NUM 0xBFF
4445
#define MBOX_MSG_GET_CAPS 0xBFD
4546
#define MBOX_MSG_GET_KVF_LIMITS 0xBFC
4647

48+
/*
49+
* Message request to config cpt lf for inline inbound ipsec.
50+
* This message is only used between CPT PF <-> CPT VF
51+
*/
52+
struct otx2_cpt_rx_inline_lf_cfg {
53+
struct mbox_msghdr hdr;
54+
u16 sso_pf_func;
55+
u16 param1;
56+
u16 param2;
57+
u16 opcode;
58+
u32 credit;
59+
u32 reserved;
60+
};
61+
4762
/*
4863
* Message request and response to get engine group number
4964
* which has attached a given type of engines (SE, AE, IE)

‎drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -141,6 +141,8 @@ int otx2_cpt_attach_rscrs_msg(struct otx2_cptlfs_info *lfs)
141141
req->hdr.sig = OTX2_MBOX_REQ_SIG;
142142
req->hdr.pcifunc = 0;
143143
req->cptlfs = lfs->lfs_num;
144+
req->cpt_blkaddr = lfs->blkaddr;
145+
req->modify = 1;
144146
ret = otx2_cpt_send_mbox_msg(mbox, lfs->pdev);
145147
if (ret)
146148
return ret;
@@ -168,6 +170,7 @@ int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs)
168170
req->hdr.id = MBOX_MSG_DETACH_RESOURCES;
169171
req->hdr.sig = OTX2_MBOX_REQ_SIG;
170172
req->hdr.pcifunc = 0;
173+
req->cptlfs = 1;
171174
ret = otx2_cpt_send_mbox_msg(mbox, lfs->pdev);
172175
if (ret)
173176
return ret;

‎drivers/crypto/marvell/octeontx2/otx2_cptlf.c‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -13,21 +13,21 @@ static void cptlf_do_set_done_time_wait(struct otx2_cptlf_info *lf,
1313
{
1414
union otx2_cptx_lf_done_wait done_wait;
1515

16-
done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
17-
OTX2_CPT_LF_DONE_WAIT);
16+
done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,
17+
lf->slot, OTX2_CPT_LF_DONE_WAIT);
1818
done_wait.s.time_wait = time_wait;
19-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
19+
otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
2020
OTX2_CPT_LF_DONE_WAIT, done_wait.u);
2121
}
2222

2323
static void cptlf_do_set_done_num_wait(struct otx2_cptlf_info *lf, int num_wait)
2424
{
2525
union otx2_cptx_lf_done_wait done_wait;
2626

27-
done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
28-
OTX2_CPT_LF_DONE_WAIT);
27+
done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,
28+
lf->slot, OTX2_CPT_LF_DONE_WAIT);
2929
done_wait.s.num_wait = num_wait;
30-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
30+
otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
3131
OTX2_CPT_LF_DONE_WAIT, done_wait.u);
3232
}
3333

@@ -147,7 +147,7 @@ static void cptlf_set_misc_intrs(struct otx2_cptlfs_info *lfs, u8 enable)
147147
irq_misc.s.nwrp = 0x1;
148148

149149
for (slot = 0; slot < lfs->lfs_num; slot++)
150-
otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot, reg,
150+
otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot, reg,
151151
irq_misc.u);
152152
}
153153

@@ -157,7 +157,7 @@ static void cptlf_enable_intrs(struct otx2_cptlfs_info *lfs)
157157

158158
/* Enable done interrupts */
159159
for (slot = 0; slot < lfs->lfs_num; slot++)
160-
otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot,
160+
otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot,
161161
OTX2_CPT_LF_DONE_INT_ENA_W1S, 0x1);
162162
/* Enable Misc interrupts */
163163
cptlf_set_misc_intrs(lfs, true);
@@ -168,7 +168,7 @@ static void cptlf_disable_intrs(struct otx2_cptlfs_info *lfs)
168168
int slot;
169169

170170
for (slot = 0; slot < lfs->lfs_num; slot++)
171-
otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot,
171+
otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot,
172172
OTX2_CPT_LF_DONE_INT_ENA_W1C, 0x1);
173173
cptlf_set_misc_intrs(lfs, false);
174174
}
@@ -177,7 +177,7 @@ static inline int cptlf_read_done_cnt(struct otx2_cptlf_info *lf)
177177
{
178178
union otx2_cptx_lf_done irq_cnt;
179179

180-
irq_cnt.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
180+
irq_cnt.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
181181
OTX2_CPT_LF_DONE);
182182
return irq_cnt.s.done;
183183
}
@@ -189,8 +189,8 @@ static irqreturn_t cptlf_misc_intr_handler(int __always_unused irq, void *arg)
189189
struct device *dev;
190190

191191
dev = &lf->lfs->pdev->dev;
192-
irq_misc.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
193-
OTX2_CPT_LF_MISC_INT);
192+
irq_misc.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,
193+
lf->slot, OTX2_CPT_LF_MISC_INT);
194194
irq_misc_ack.u = 0x0;
195195

196196
if (irq_misc.s.fault) {
@@ -222,7 +222,7 @@ static irqreturn_t cptlf_misc_intr_handler(int __always_unused irq, void *arg)
222222
}
223223

224224
/* Acknowledge interrupts */
225-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
225+
otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
226226
OTX2_CPT_LF_MISC_INT, irq_misc_ack.u);
227227

228228
return IRQ_HANDLED;
@@ -237,13 +237,13 @@ static irqreturn_t cptlf_done_intr_handler(int irq, void *arg)
237237
/* Read the number of completed requests */
238238
irq_cnt = cptlf_read_done_cnt(lf);
239239
if (irq_cnt) {
240-
done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0,
240+
done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,
241241
lf->slot, OTX2_CPT_LF_DONE_WAIT);
242242
/* Acknowledge the number of completed requests */
243-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
243+
otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
244244
OTX2_CPT_LF_DONE_ACK, irq_cnt);
245245

246-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
246+
otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
247247
OTX2_CPT_LF_DONE_WAIT, done_wait.u);
248248
if (unlikely(!lf->wqe)) {
249249
dev_err(&lf->lfs->pdev->dev, "No work for LF %d\n",
@@ -393,7 +393,7 @@ int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_mask, int pri,
393393
OTX2_CPT_LMT_LF_LMTLINEX(0));
394394

395395
lfs->lf[slot].ioreg = lfs->reg_base +
396-
OTX2_CPT_RVU_FUNC_ADDR_S(BLKADDR_CPT0, slot,
396+
OTX2_CPT_RVU_FUNC_ADDR_S(lfs->blkaddr, slot,
397397
OTX2_CPT_LF_NQX(0));
398398
}
399399
/* Send request to attach LFs */

‎drivers/crypto/marvell/octeontx2/otx2_cptlf.h‎

Lines changed: 24 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -180,7 +180,7 @@ static inline void otx2_cptlf_set_iqueues_base_addr(
180180

181181
for (slot = 0; slot < lfs->lfs_num; slot++) {
182182
lf_q_base.u = lfs->lf[slot].iqueue.dma_addr;
183-
otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot,
183+
otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot,
184184
OTX2_CPT_LF_Q_BASE, lf_q_base.u);
185185
}
186186
}
@@ -191,7 +191,7 @@ static inline void otx2_cptlf_do_set_iqueue_size(struct otx2_cptlf_info *lf)
191191

192192
lf_q_size.s.size_div40 = OTX2_CPT_SIZE_DIV40 +
193193
OTX2_CPT_EXTRA_SIZE_DIV40;
194-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
194+
otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
195195
OTX2_CPT_LF_Q_SIZE, lf_q_size.u);
196196
}
197197

@@ -207,15 +207,16 @@ static inline void otx2_cptlf_do_disable_iqueue(struct otx2_cptlf_info *lf)
207207
{
208208
union otx2_cptx_lf_ctl lf_ctl = { .u = 0x0 };
209209
union otx2_cptx_lf_inprog lf_inprog;
210+
u8 blkaddr = lf->lfs->blkaddr;
210211
int timeout = 20;
211212

212213
/* Disable instructions enqueuing */
213-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
214+
otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,
214215
OTX2_CPT_LF_CTL, lf_ctl.u);
215216

216217
/* Wait for instruction queue to become empty */
217218
do {
218-
lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0,
219+
lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, blkaddr,
219220
lf->slot, OTX2_CPT_LF_INPROG);
220221
if (!lf_inprog.s.inflight)
221222
break;
@@ -234,7 +235,7 @@ static inline void otx2_cptlf_do_disable_iqueue(struct otx2_cptlf_info *lf)
234235
* the queue should be empty at this point
235236
*/
236237
lf_inprog.s.eena = 0x0;
237-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
238+
otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,
238239
OTX2_CPT_LF_INPROG, lf_inprog.u);
239240
}
240241

@@ -249,14 +250,15 @@ static inline void otx2_cptlf_disable_iqueues(struct otx2_cptlfs_info *lfs)
249250
static inline void otx2_cptlf_set_iqueue_enq(struct otx2_cptlf_info *lf,
250251
bool enable)
251252
{
253+
u8 blkaddr = lf->lfs->blkaddr;
252254
union otx2_cptx_lf_ctl lf_ctl;
253255

254-
lf_ctl.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
256+
lf_ctl.u = otx2_cpt_read64(lf->lfs->reg_base, blkaddr, lf->slot,
255257
OTX2_CPT_LF_CTL);
256258

257259
/* Set iqueue's enqueuing */
258260
lf_ctl.s.ena = enable ? 0x1 : 0x0;
259-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
261+
otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,
260262
OTX2_CPT_LF_CTL, lf_ctl.u);
261263
}
262264

@@ -269,13 +271,14 @@ static inline void otx2_cptlf_set_iqueue_exec(struct otx2_cptlf_info *lf,
269271
bool enable)
270272
{
271273
union otx2_cptx_lf_inprog lf_inprog;
274+
u8 blkaddr = lf->lfs->blkaddr;
272275

273-
lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
276+
lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, blkaddr, lf->slot,
274277
OTX2_CPT_LF_INPROG);
275278

276279
/* Set iqueue's execution */
277280
lf_inprog.s.eena = enable ? 0x1 : 0x0;
278-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
281+
otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,
279282
OTX2_CPT_LF_INPROG, lf_inprog.u);
280283
}
281284

@@ -364,6 +367,18 @@ static inline bool otx2_cptlf_started(struct otx2_cptlfs_info *lfs)
364367
return atomic_read(&lfs->state) == OTX2_CPTLF_STARTED;
365368
}
366369

370+
static inline void otx2_cptlf_set_dev_info(struct otx2_cptlfs_info *lfs,
371+
struct pci_dev *pdev,
372+
void __iomem *reg_base,
373+
struct otx2_mbox *mbox,
374+
int blkaddr)
375+
{
376+
lfs->pdev = pdev;
377+
lfs->reg_base = reg_base;
378+
lfs->mbox = mbox;
379+
lfs->blkaddr = blkaddr;
380+
}
381+
367382
int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_msk, int pri,
368383
int lfs_num);
369384
void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs);

‎drivers/crypto/marvell/octeontx2/otx2_cptpf.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ struct otx2_cptpf_dev {
3131
struct otx2_cptvf_info vf[OTX2_CPT_MAX_VFS_NUM];
3232
struct otx2_cpt_eng_grps eng_grps;/* Engine groups information */
3333
struct otx2_cptlfs_info lfs; /* CPT LFs attached to this PF */
34+
struct otx2_cptlfs_info cpt1_lfs; /* CPT1 LFs attached to this PF */
3435
/* HW capabilities for each engine type */
3536
union otx2_cpt_eng_caps eng_caps[OTX2_CPT_MAX_ENG_TYPES];
3637
bool is_eng_caps_discovered;
@@ -55,8 +56,10 @@ struct otx2_cptpf_dev {
5556
u8 pf_id; /* RVU PF number */
5657
u8 max_vfs; /* Maximum number of VFs supported by CPT */
5758
u8 enabled_vfs; /* Number of enabled VFs */
59+
u8 sso_pf_func_ovrd; /* SSO PF_FUNC override bit */
5860
u8 kvf_limits; /* Kernel crypto limits */
5961
bool has_cpt1;
62+
u8 rsrc_req_blkaddr;
6063

6164
/* Devlink */
6265
struct devlink *dl;

‎drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,8 @@
1313
#define OTX2_CPT_DRV_NAME "rvu_cptpf"
1414
#define OTX2_CPT_DRV_STRING "Marvell RVU CPT Physical Function Driver"
1515

16+
#define CPT_UC_RID_CN9K_B0 1
17+
1618
static void cptpf_enable_vfpf_mbox_intr(struct otx2_cptpf_dev *cptpf,
1719
int num_vfs)
1820
{
@@ -498,6 +500,32 @@ static void cptpf_afpf_mbox_destroy(struct otx2_cptpf_dev *cptpf)
498500
otx2_mbox_destroy(&cptpf->afpf_mbox_up);
499501
}
500502

503+
static ssize_t sso_pf_func_ovrd_show(struct device *dev,
504+
struct device_attribute *attr, char *buf)
505+
{
506+
struct otx2_cptpf_dev *cptpf = dev_get_drvdata(dev);
507+
508+
return sprintf(buf, "%d\n", cptpf->sso_pf_func_ovrd);
509+
}
510+
511+
static ssize_t sso_pf_func_ovrd_store(struct device *dev,
512+
struct device_attribute *attr,
513+
const char *buf, size_t count)
514+
{
515+
struct otx2_cptpf_dev *cptpf = dev_get_drvdata(dev);
516+
u8 sso_pf_func_ovrd;
517+
518+
if (!(cptpf->pdev->revision == CPT_UC_RID_CN9K_B0))
519+
return count;
520+
521+
if (kstrtou8(buf, 0, &sso_pf_func_ovrd))
522+
return -EINVAL;
523+
524+
cptpf->sso_pf_func_ovrd = sso_pf_func_ovrd;
525+
526+
return count;
527+
}
528+
501529
static ssize_t kvf_limits_show(struct device *dev,
502530
struct device_attribute *attr, char *buf)
503531
{
@@ -528,8 +556,11 @@ static ssize_t kvf_limits_store(struct device *dev,
528556
}
529557

530558
static DEVICE_ATTR_RW(kvf_limits);
559+
static DEVICE_ATTR_RW(sso_pf_func_ovrd);
560+
531561
static struct attribute *cptpf_attrs[] = {
532562
&dev_attr_kvf_limits.attr,
563+
&dev_attr_sso_pf_func_ovrd.attr,
533564
NULL
534565
};
535566

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