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drm/xe: Implement madvise ioctl for xe
This driver-specific ioctl enables UMDs to control the memory attributes for GPU VMAs within a specified input range. If the start or end addresses fall within an existing VMA, the VMA is split accordingly. The attributes of the VMA are modified as provided by the users. The old mappings of the VMAs are invalidated, and TLB invalidation is performed if necessary. v2(Matthew brost) - xe_vm_in_fault_mode can't be enabled by Mesa, hence allow ioctl in non fault mode too - fix tlb invalidation skip for same ranges in multiple op - use helper for tlb invalidation - use xe_svm_notifier_lock/unlock helper - s/lockdep_assert_held/lockdep_assert_held_write - Add kernel-doc v3(Matthew Brost) - make vfunc fail safe - Add sanitizing input args before vfunc v4(Matthew Brost/Shuicheng) - Make locks interruptable - Error handling fixes - vm_put fixes v5(Matthew Brost) - Flush garbage collector before any locking. - Add check for null vma Cc: Matthew Brost <matthew.brost@intel.com> Cc: Shuicheng Lin <shuicheng.lin@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://lore.kernel.org/r/20250821173104.3030148-9-himal.prasad.ghimiray@intel.com Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
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‎drivers/gpu/drm/xe/Makefile‎

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@@ -129,6 +129,7 @@ xe-y += xe_bb.o \
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xe_uc.o \
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xe_uc_fw.o \
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xe_vm.o \
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xe_vm_madvise.o \
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xe_vram.o \
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xe_vram_freq.o \
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xe_vsec.o \

‎drivers/gpu/drm/xe/xe_vm_madvise.c‎

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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2025 Intel Corporation
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*/
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#include "xe_vm_madvise.h"
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#include <linux/nospec.h>
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#include <drm/xe_drm.h>
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#include "xe_bo.h"
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#include "xe_pt.h"
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#include "xe_svm.h"
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struct xe_vmas_in_madvise_range {
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u64 addr;
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u64 range;
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struct xe_vma **vmas;
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int num_vmas;
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bool has_svm_vmas;
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bool has_bo_vmas;
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bool has_userptr_vmas;
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};
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static int get_vmas(struct xe_vm *vm, struct xe_vmas_in_madvise_range *madvise_range)
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{
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u64 addr = madvise_range->addr;
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u64 range = madvise_range->range;
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struct xe_vma **__vmas;
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struct drm_gpuva *gpuva;
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int max_vmas = 8;
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lockdep_assert_held(&vm->lock);
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madvise_range->num_vmas = 0;
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madvise_range->vmas = kmalloc_array(max_vmas, sizeof(*madvise_range->vmas), GFP_KERNEL);
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if (!madvise_range->vmas)
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return -ENOMEM;
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vm_dbg(&vm->xe->drm, "VMA's in range: start=0x%016llx, end=0x%016llx", addr, addr + range);
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drm_gpuvm_for_each_va_range(gpuva, &vm->gpuvm, addr, addr + range) {
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struct xe_vma *vma = gpuva_to_vma(gpuva);
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if (xe_vma_bo(vma))
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madvise_range->has_bo_vmas = true;
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else if (xe_vma_is_cpu_addr_mirror(vma))
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madvise_range->has_svm_vmas = true;
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else if (xe_vma_is_userptr(vma))
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madvise_range->has_userptr_vmas = true;
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if (madvise_range->num_vmas == max_vmas) {
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max_vmas <<= 1;
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__vmas = krealloc(madvise_range->vmas,
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max_vmas * sizeof(*madvise_range->vmas),
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GFP_KERNEL);
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if (!__vmas) {
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kfree(madvise_range->vmas);
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return -ENOMEM;
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}
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madvise_range->vmas = __vmas;
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}
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madvise_range->vmas[madvise_range->num_vmas] = vma;
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(madvise_range->num_vmas)++;
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}
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if (!madvise_range->num_vmas)
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kfree(madvise_range->vmas);
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vm_dbg(&vm->xe->drm, "madvise_range-num_vmas = %d\n", madvise_range->num_vmas);
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return 0;
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}
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static void madvise_preferred_mem_loc(struct xe_device *xe, struct xe_vm *vm,
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struct xe_vma **vmas, int num_vmas,
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struct drm_xe_madvise *op)
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{
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/* Implementation pending */
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}
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static void madvise_atomic(struct xe_device *xe, struct xe_vm *vm,
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struct xe_vma **vmas, int num_vmas,
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struct drm_xe_madvise *op)
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{
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/* Implementation pending */
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}
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static void madvise_pat_index(struct xe_device *xe, struct xe_vm *vm,
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struct xe_vma **vmas, int num_vmas,
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struct drm_xe_madvise *op)
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{
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/* Implementation pending */
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}
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typedef void (*madvise_func)(struct xe_device *xe, struct xe_vm *vm,
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struct xe_vma **vmas, int num_vmas,
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struct drm_xe_madvise *op);
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static const madvise_func madvise_funcs[] = {
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[DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC] = madvise_preferred_mem_loc,
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[DRM_XE_MEM_RANGE_ATTR_ATOMIC] = madvise_atomic,
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[DRM_XE_MEM_RANGE_ATTR_PAT] = madvise_pat_index,
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};
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static u8 xe_zap_ptes_in_madvise_range(struct xe_vm *vm, u64 start, u64 end)
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{
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struct drm_gpuva *gpuva;
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struct xe_tile *tile;
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u8 id, tile_mask;
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lockdep_assert_held_write(&vm->lock);
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/* Wait for pending binds */
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if (dma_resv_wait_timeout(xe_vm_resv(vm), DMA_RESV_USAGE_BOOKKEEP,
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false, MAX_SCHEDULE_TIMEOUT) <= 0)
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XE_WARN_ON(1);
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tile_mask = xe_svm_ranges_zap_ptes_in_range(vm, start, end);
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drm_gpuvm_for_each_va_range(gpuva, &vm->gpuvm, start, end) {
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struct xe_vma *vma = gpuva_to_vma(gpuva);
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if (xe_vma_is_cpu_addr_mirror(vma) || xe_vma_is_null(vma))
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continue;
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for_each_tile(tile, vm->xe, id) {
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if (xe_pt_zap_ptes(tile, vma)) {
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tile_mask |= BIT(id);
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/*
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* WRITE_ONCE pairs with READ_ONCE
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* in xe_vm_has_valid_gpu_mapping()
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*/
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WRITE_ONCE(vma->tile_invalidated,
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vma->tile_invalidated | BIT(id));
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}
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}
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}
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return tile_mask;
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}
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static int xe_vm_invalidate_madvise_range(struct xe_vm *vm, u64 start, u64 end)
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{
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u8 tile_mask = xe_zap_ptes_in_madvise_range(vm, start, end);
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if (!tile_mask)
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return 0;
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xe_device_wmb(vm->xe);
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return xe_vm_range_tilemask_tlb_invalidation(vm, start, end, tile_mask);
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}
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static bool madvise_args_are_sane(struct xe_device *xe, const struct drm_xe_madvise *args)
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{
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if (XE_IOCTL_DBG(xe, !args))
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return false;
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if (XE_IOCTL_DBG(xe, !IS_ALIGNED(args->start, SZ_4K)))
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return false;
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if (XE_IOCTL_DBG(xe, !IS_ALIGNED(args->range, SZ_4K)))
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return false;
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if (XE_IOCTL_DBG(xe, args->range < SZ_4K))
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return false;
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switch (args->type) {
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case DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC:
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if (XE_IOCTL_DBG(xe, args->preferred_mem_loc.migration_policy >
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DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES))
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return false;
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if (XE_IOCTL_DBG(xe, args->preferred_mem_loc.pad))
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return false;
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if (XE_IOCTL_DBG(xe, args->atomic.reserved))
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return false;
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break;
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case DRM_XE_MEM_RANGE_ATTR_ATOMIC:
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if (XE_IOCTL_DBG(xe, args->atomic.val > DRM_XE_ATOMIC_CPU))
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return false;
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if (XE_IOCTL_DBG(xe, args->atomic.pad))
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return false;
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if (XE_IOCTL_DBG(xe, args->atomic.reserved))
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return false;
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break;
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case DRM_XE_MEM_RANGE_ATTR_PAT:
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/*TODO: Add valid pat check */
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break;
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default:
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if (XE_IOCTL_DBG(xe, 1))
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return false;
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}
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if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
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return false;
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return true;
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}
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/**
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* xe_vm_madvise_ioctl - Handle MADVise ioctl for a VM
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* @dev: DRM device pointer
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* @data: Pointer to ioctl data (drm_xe_madvise*)
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* @file: DRM file pointer
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*
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* Handles the MADVISE ioctl to provide memory advice for vma's within
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* input range.
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*
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* Return: 0 on success or a negative error code on failure.
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*/
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int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
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{
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struct xe_device *xe = to_xe_device(dev);
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struct xe_file *xef = to_xe_file(file);
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struct drm_xe_madvise *args = data;
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struct xe_vmas_in_madvise_range madvise_range = {.addr = args->start,
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.range = args->range, };
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struct xe_vm *vm;
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struct drm_exec exec;
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int err, attr_type;
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vm = xe_vm_lookup(xef, args->vm_id);
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if (XE_IOCTL_DBG(xe, !vm))
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return -EINVAL;
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if (!madvise_args_are_sane(vm->xe, args)) {
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err = -EINVAL;
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goto put_vm;
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}
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xe_svm_flush(vm);
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err = down_write_killable(&vm->lock);
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if (err)
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goto put_vm;
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if (XE_IOCTL_DBG(xe, xe_vm_is_closed_or_banned(vm))) {
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err = -ENOENT;
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goto unlock_vm;
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}
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err = xe_vm_alloc_madvise_vma(vm, args->start, args->range);
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if (err)
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goto unlock_vm;
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err = get_vmas(vm, &madvise_range);
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if (err || !madvise_range.num_vmas)
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goto unlock_vm;
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if (madvise_range.has_bo_vmas) {
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drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES | DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
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drm_exec_until_all_locked(&exec) {
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for (int i = 0; i < madvise_range.num_vmas; i++) {
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struct xe_bo *bo = xe_vma_bo(madvise_range.vmas[i]);
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if (!bo)
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continue;
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err = drm_exec_lock_obj(&exec, &bo->ttm.base);
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drm_exec_retry_on_contention(&exec);
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if (err)
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goto err_fini;
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}
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}
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}
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if (madvise_range.has_userptr_vmas) {
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err = down_read_interruptible(&vm->userptr.notifier_lock);
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if (err)
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goto err_fini;
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}
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if (madvise_range.has_svm_vmas) {
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err = down_read_interruptible(&vm->svm.gpusvm.notifier_lock);
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if (err)
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goto unlock_userptr;
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}
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attr_type = array_index_nospec(args->type, ARRAY_SIZE(madvise_funcs));
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madvise_funcs[attr_type](xe, vm, madvise_range.vmas, madvise_range.num_vmas, args);
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err = xe_vm_invalidate_madvise_range(vm, args->start, args->start + args->range);
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if (madvise_range.has_svm_vmas)
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xe_svm_notifier_unlock(vm);
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unlock_userptr:
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if (madvise_range.has_userptr_vmas)
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up_read(&vm->userptr.notifier_lock);
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err_fini:
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if (madvise_range.has_bo_vmas)
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drm_exec_fini(&exec);
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kfree(madvise_range.vmas);
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madvise_range.vmas = NULL;
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unlock_vm:
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up_write(&vm->lock);
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put_vm:
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xe_vm_put(vm);
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return err;
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}

‎drivers/gpu/drm/xe/xe_vm_madvise.h‎

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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2025 Intel Corporation
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*/
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#ifndef _XE_VM_MADVISE_H_
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#define _XE_VM_MADVISE_H_
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struct drm_device;
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struct drm_file;
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int xe_vm_madvise_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file);
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#endif

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