drm/amd/amdgpu: Update RLC_SPM_MC_CNT by ring wreg in guest

YuanShang · alexdeucher · commit b5387349cadd · 2024-01-18T15:45:58.000-05:00
Submit command of wreg in GFX and COMPUTE ring to update
RLC_SPM_MC_CNT in guest machine during runtime.

Signed-off-by: YuanShang &lt;YuanShang.Mao@amd.com&gt;
Reviewed-by: Emily Deng &lt;Emily.Deng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
@@ -169,7 +169,7 @@ struct amdgpu_rlc_funcs {
 	void (*stop)(struct amdgpu_device *adev);
 	void (*reset)(struct amdgpu_device *adev);
 	void (*start)(struct amdgpu_device *adev);
-	void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid);
+	void (*update_spm_vmid)(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid);
 	bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -693,7 +693,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
 		amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
 
 	if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)
-		adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
+		adev->gfx.rlc.funcs->update_spm_vmid(adev, ring, job->vmid);
 
 	if (!ring->is_mes_queue && ring->funcs->emit_gds_switch &&
 	    gds_switch_needed) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7949,7 +7949,7 @@ static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
 	WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
 }
 
-static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid)
+static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
 {
 	amdgpu_gfx_off_ctrl(adev, false);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -749,7 +749,7 @@ static int gfx_v11_0_rlc_init(struct amdgpu_device *adev)
 
 	/* init spm vmid with 0xf */
 	if (adev->gfx.rlc.funcs->update_spm_vmid)
-		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
+		adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
 
 	return 0;
 }
@@ -5049,7 +5049,7 @@ static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
 	return 0;
 }
 
-static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
+static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid)
 {
 	u32 data;
 
@@ -5063,6 +5063,14 @@ static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
 	WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
 
 	amdgpu_gfx_off_ctrl(adev, true);
+
+	if (ring
+		&& amdgpu_sriov_is_pp_one_vf(adev)
+		&& ((ring->funcs->type == AMDGPU_RING_TYPE_GFX)
+			|| (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
+		uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
+		amdgpu_ring_emit_wreg(ring, reg, data);
+	}
 }
 
 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = {
@@ -6126,7 +6134,8 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
 	.get_rptr = gfx_v11_0_ring_get_rptr_gfx,
 	.get_wptr = gfx_v11_0_ring_get_wptr_gfx,
 	.set_wptr = gfx_v11_0_ring_set_wptr_gfx,
-	.emit_frame_size = /* totally 242 maximum if 16 IBs */
+	.emit_frame_size = /* totally 247 maximum if 16 IBs */
+		5 + /* update_spm_vmid */
 		5 + /* COND_EXEC */
 		9 + /* SET_Q_PREEMPTION_MODE */
 		7 + /* PIPELINE_SYNC */
@@ -6176,6 +6185,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {
 	.get_wptr = gfx_v11_0_ring_get_wptr_compute,
 	.set_wptr = gfx_v11_0_ring_set_wptr_compute,
 	.emit_frame_size =
+		5 + /* update_spm_vmid */
 		20 + /* gfx_v11_0_ring_emit_gds_switch */
 		7 + /* gfx_v11_0_ring_emit_hdp_flush */
 		5 + /* hdp invalidate */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3274,7 +3274,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
 
 	/* init spm vmid with 0xf */
 	if (adev->gfx.rlc.funcs->update_spm_vmid)
-		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
+		adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
 
 	return 0;
 }
@@ -3500,7 +3500,7 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
 	return 0;
 }
 
-static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
+static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid)
 {
 	u32 data;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1288,7 +1288,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
 
 	/* init spm vmid with 0xf */
 	if (adev->gfx.rlc.funcs->update_spm_vmid)
-		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
+		adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
 
 	return 0;
 }
@@ -5579,7 +5579,7 @@ static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
 	}
 }
 
-static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
+static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid)
 {
 	u32 data;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4894,7 +4894,7 @@ static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev,
 		WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
 }
 
-static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid)
+static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
 {
 	amdgpu_gfx_off_ctrl(adev, false);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -1174,7 +1174,7 @@ static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev)
 {
 	/* init spm vmid with 0xf */
 	if (adev->gfx.rlc.funcs->update_spm_vmid)
-		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
+		adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
 
 	return 0;
 }
@@ -1385,7 +1385,7 @@ static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev)
 	return 0;
 }
 
-static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev,
+static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring,
 				       unsigned vmid)
 {
 	u32 reg, data;

Original file line number	Diff line number	Diff line change
`@@ -7949,7 +7949,7 @@ static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,`
`7949`	`7949`	`WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);`
`7950`	`7950`	`}`
`7951`	`7951`
`7952`		`-static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid)`
	`7952`	`+static void gfx_v10_0_update_spm_vmid(struct amdgpu_device adev, struct amdgpu_ring ring, unsigned int vmid)`
`7953`	`7953`	`{`
`7954`	`7954`	`amdgpu_gfx_off_ctrl(adev, false);`
`7955`	`7955`
Original file line number	Diff line number	Diff line change
`@@ -3274,7 +3274,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)`
`3274`	`3274`
`3275`	`3275`	`/* init spm vmid with 0xf */`
`3276`	`3276`	`if (adev->gfx.rlc.funcs->update_spm_vmid)`
`3277`		`- adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);`
	`3277`	`+ adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);`
`3278`	`3278`
`3279`	`3279`	`return 0;`
`3280`	`3280`	`}`
`@@ -3500,7 +3500,7 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)`
`3500`	`3500`	`return 0;`
`3501`	`3501`	`}`
`3502`	`3502`
`3503`		`-static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)`
	`3503`	`+static void gfx_v7_0_update_spm_vmid(struct amdgpu_device adev, struct amdgpu_ring ring, unsigned vmid)`
`3504`	`3504`	`{`
`3505`	`3505`	`u32 data;`
`3506`	`3506`
Original file line number	Diff line number	Diff line change
`@@ -1288,7 +1288,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)`
`1288`	`1288`
`1289`	`1289`	`/* init spm vmid with 0xf */`
`1290`	`1290`	`if (adev->gfx.rlc.funcs->update_spm_vmid)`
`1291`		`- adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);`
	`1291`	`+ adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);`
`1292`	`1292`
`1293`	`1293`	`return 0;`
`1294`	`1294`	`}`
`@@ -5579,7 +5579,7 @@ static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)`
`5579`	`5579`	`}`
`5580`	`5580`	`}`
`5581`	`5581`
`5582`		`-static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)`
	`5582`	`+static void gfx_v8_0_update_spm_vmid(struct amdgpu_device adev, struct amdgpu_ring ring, unsigned vmid)`
`5583`	`5583`	`{`
`5584`	`5584`	`u32 data;`
`5585`	`5585`
Original file line number	Diff line number	Diff line change
`@@ -4894,7 +4894,7 @@ static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev,`
`4894`	`4894`	`WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);`
`4895`	`4895`	`}`
`4896`	`4896`
`4897`		`-static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid)`
	`4897`	`+static void gfx_v9_0_update_spm_vmid(struct amdgpu_device adev, struct amdgpu_ring ring, unsigned int vmid)`
`4898`	`4898`	`{`
`4899`	`4899`	`amdgpu_gfx_off_ctrl(adev, false);`
`4900`	`4900`
Original file line number	Diff line number	Diff line change
`@@ -1174,7 +1174,7 @@ static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev)`
`1174`	`1174`	`{`
`1175`	`1175`	`/* init spm vmid with 0xf */`
`1176`	`1176`	`if (adev->gfx.rlc.funcs->update_spm_vmid)`
`1177`		`- adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);`
	`1177`	`+ adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);`
`1178`	`1178`
`1179`	`1179`	`return 0;`
`1180`	`1180`	`}`
`@@ -1385,7 +1385,7 @@ static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev)`
`1385`	`1385`	`return 0;`
`1386`	`1386`	`}`
`1387`	`1387`
`1388`		`-static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev,`
	`1388`	`+static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device adev, struct amdgpu_ring ring,`
`1389`	`1389`	`unsigned vmid)`
`1390`	`1390`	`{`
`1391`	`1391`	`u32 reg, data;`