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Merge branch 'mlxsw-Add-support-for-new-port-types-and-speeds-for-Spectrum-2'
Ido Schimmel says: ==================== mlxsw: Add support for new port types and speeds for Spectrum-2 Shalom says: This patchset adds support for new port types and speeds for Spectrum-2. Patch #1 + #2 removes an unsupported PTYS field and a duplicate link mode entry. Patch #3 queries port's connector type from firmware instead of deriving it from port admin state. Patch #4 renames functions which relate to port type-speed to be Spectrum-1 specific. Patch #5 defines port type-speed operations and applies it for Spectrum-1. Patch #6 + #7 are small renaming and cosmetic changes. Patch #8 adds new port type-speed fields for PTYS register. These new fields extend the existing ones in order to support more types and speeds. Patch #9 adds Spectrum-2 support for port type-speed operations. Patch #10 adds Spectrum-2 new port types and speeds. For Spectrum-2, the user must configure all the types per speed if he / she wants a specific speed to be advertised. For example, if the user wants to advertise 100Gbps 4-lanes speed, the following ethtool bits should be advertised: Supported ethtool bits for 100Gbps 4-lanes: 0x1000000000 100000baseKR4 Full 0x2000000000 100000baseSR4 Full 0x4000000000 100000baseCR4 Full 0x8000000000 100000baseLR4_ER4 Full Command for advertising 100Gbps 4-lanes: ethtool -s enp3s0np1 advertise 0xF000000000 ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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‎drivers/net/ethernet/mellanox/mlxsw/reg.h‎

Lines changed: 80 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3971,6 +3971,25 @@ enum {
39713971
*/
39723972
MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
39733973

3974+
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0)
3975+
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1)
3976+
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII BIT(2)
3977+
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3)
3978+
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4)
3979+
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5)
3980+
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6)
3981+
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7)
3982+
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8)
3983+
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9)
3984+
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10)
3985+
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12)
3986+
3987+
/* reg_ptys_ext_eth_proto_cap
3988+
* Extended Ethernet port supported speeds and protocols.
3989+
* Access: RO
3990+
*/
3991+
MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
3992+
39743993
#define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
39753994
#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
39763995
#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
@@ -4025,6 +4044,12 @@ MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16);
40254044
*/
40264045
MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
40274046

4047+
/* reg_ptys_ext_eth_proto_admin
4048+
* Extended speed and protocol to set port to.
4049+
* Access: RW
4050+
*/
4051+
MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
4052+
40284053
/* reg_ptys_eth_proto_admin
40294054
* Speed and protocol to set port to.
40304055
* Access: RW
@@ -4043,6 +4068,12 @@ MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16);
40434068
*/
40444069
MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
40454070

4071+
/* reg_ptys_ext_eth_proto_oper
4072+
* The extended current speed and protocol configured for the port.
4073+
* Access: RO
4074+
*/
4075+
MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
4076+
40464077
/* reg_ptys_eth_proto_oper
40474078
* The current speed and protocol configured for the port.
40484079
* Access: RO
@@ -4061,12 +4092,23 @@ MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16);
40614092
*/
40624093
MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
40634094

4064-
/* reg_ptys_eth_proto_lp_advertise
4065-
* The protocols that were advertised by the link partner during
4066-
* autonegotiation.
4095+
enum mlxsw_reg_ptys_connector_type {
4096+
MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR,
4097+
MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE,
4098+
MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP,
4099+
MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI,
4100+
MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC,
4101+
MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII,
4102+
MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE,
4103+
MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA,
4104+
MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER,
4105+
};
4106+
4107+
/* reg_ptys_connector_type
4108+
* Connector type indication.
40674109
* Access: RO
40684110
*/
4069-
MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32);
4111+
MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
40704112

40714113
static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port,
40724114
u32 proto_admin, bool autoneg)
@@ -4078,17 +4120,46 @@ static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port,
40784120
mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
40794121
}
40804122

4123+
static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port,
4124+
u32 proto_admin, bool autoneg)
4125+
{
4126+
MLXSW_REG_ZERO(ptys, payload);
4127+
mlxsw_reg_ptys_local_port_set(payload, local_port);
4128+
mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4129+
mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);
4130+
mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4131+
}
4132+
40814133
static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
40824134
u32 *p_eth_proto_cap,
4083-
u32 *p_eth_proto_adm,
4135+
u32 *p_eth_proto_admin,
40844136
u32 *p_eth_proto_oper)
40854137
{
40864138
if (p_eth_proto_cap)
4087-
*p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
4088-
if (p_eth_proto_adm)
4089-
*p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
4139+
*p_eth_proto_cap =
4140+
mlxsw_reg_ptys_eth_proto_cap_get(payload);
4141+
if (p_eth_proto_admin)
4142+
*p_eth_proto_admin =
4143+
mlxsw_reg_ptys_eth_proto_admin_get(payload);
4144+
if (p_eth_proto_oper)
4145+
*p_eth_proto_oper =
4146+
mlxsw_reg_ptys_eth_proto_oper_get(payload);
4147+
}
4148+
4149+
static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload,
4150+
u32 *p_eth_proto_cap,
4151+
u32 *p_eth_proto_admin,
4152+
u32 *p_eth_proto_oper)
4153+
{
4154+
if (p_eth_proto_cap)
4155+
*p_eth_proto_cap =
4156+
mlxsw_reg_ptys_ext_eth_proto_cap_get(payload);
4157+
if (p_eth_proto_admin)
4158+
*p_eth_proto_admin =
4159+
mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);
40904160
if (p_eth_proto_oper)
4091-
*p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
4161+
*p_eth_proto_oper =
4162+
mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
40924163
}
40934164

40944165
static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port,

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