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Bibby Hsiehckhu-mediatek
Bibby Hsieh
authored and
ckhu-mediatek
committed
drm/mediatek: support CMDQ interface in ddp component
The CMDQ (Command Queue) in some Mediatek SoC is used to help update all relevant display controller registers with critical time limation. This patch add cmdq interface in ddp_comp interface, let all ddp_comp interface can support cpu/cmdq function at the same time. Signed-off-by: YT Shen <yt.shen@mediatek.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
1 parent 17aab65 commit d0afe37

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6 files changed

+186
-94
lines changed

6 files changed

+186
-94
lines changed

‎drivers/gpu/drm/mediatek/mtk_disp_color.c‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#include <linux/of_device.h>
1010
#include <linux/of_irq.h>
1111
#include <linux/platform_device.h>
12+
#include <linux/soc/mediatek/mtk-cmdq.h>
1213

1314
#include "mtk_drm_crtc.h"
1415
#include "mtk_drm_ddp_comp.h"
@@ -45,12 +46,12 @@ static inline struct mtk_disp_color *comp_to_color(struct mtk_ddp_comp *comp)
4546

4647
static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
4748
unsigned int h, unsigned int vrefresh,
48-
unsigned int bpc)
49+
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
4950
{
5051
struct mtk_disp_color *color = comp_to_color(comp);
5152

52-
writel(w, comp->regs + DISP_COLOR_WIDTH(color));
53-
writel(h, comp->regs + DISP_COLOR_HEIGHT(color));
53+
mtk_ddp_write(cmdq_pkt, w, comp, DISP_COLOR_WIDTH(color));
54+
mtk_ddp_write(cmdq_pkt, h, comp, DISP_COLOR_HEIGHT(color));
5455
}
5556

5657
static void mtk_color_start(struct mtk_ddp_comp *comp)

‎drivers/gpu/drm/mediatek/mtk_disp_ovl.c‎

Lines changed: 35 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#include <linux/of_device.h>
1212
#include <linux/of_irq.h>
1313
#include <linux/platform_device.h>
14+
#include <linux/soc/mediatek/mtk-cmdq.h>
1415

1516
#include "mtk_drm_crtc.h"
1617
#include "mtk_drm_ddp_comp.h"
@@ -124,14 +125,15 @@ static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
124125

125126
static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,
126127
unsigned int h, unsigned int vrefresh,
127-
unsigned int bpc)
128+
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
128129
{
129130
if (w != 0 && h != 0)
130-
writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE);
131-
writel_relaxed(0x0, comp->regs + DISP_REG_OVL_ROI_BGCLR);
131+
mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, comp,
132+
DISP_REG_OVL_ROI_SIZE);
133+
mtk_ddp_write_relaxed(cmdq_pkt, 0x0, comp, DISP_REG_OVL_ROI_BGCLR);
132134

133-
writel(0x1, comp->regs + DISP_REG_OVL_RST);
134-
writel(0x0, comp->regs + DISP_REG_OVL_RST);
135+
mtk_ddp_write(cmdq_pkt, 0x1, comp, DISP_REG_OVL_RST);
136+
mtk_ddp_write(cmdq_pkt, 0x0, comp, DISP_REG_OVL_RST);
135137
}
136138

137139
static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp)
@@ -175,16 +177,16 @@ static int mtk_ovl_layer_check(struct mtk_ddp_comp *comp, unsigned int idx,
175177
return 0;
176178
}
177179

178-
static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
180+
static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx,
181+
struct cmdq_pkt *cmdq_pkt)
179182
{
180-
unsigned int reg;
181183
unsigned int gmc_thrshd_l;
182184
unsigned int gmc_thrshd_h;
183185
unsigned int gmc_value;
184186
struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
185187

186-
writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
187-
188+
mtk_ddp_write(cmdq_pkt, 0x1, comp,
189+
DISP_REG_OVL_RDMA_CTRL(idx));
188190
gmc_thrshd_l = GMC_THRESHOLD_LOW >>
189191
(GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
190192
gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
@@ -194,22 +196,19 @@ static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
194196
else
195197
gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |
196198
gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
197-
writel(gmc_value, comp->regs + DISP_REG_OVL_RDMA_GMC(idx));
198-
199-
reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
200-
reg = reg | BIT(idx);
201-
writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
199+
mtk_ddp_write(cmdq_pkt, gmc_value,
200+
comp, DISP_REG_OVL_RDMA_GMC(idx));
201+
mtk_ddp_write_mask(cmdq_pkt, BIT(idx), comp,
202+
DISP_REG_OVL_SRC_CON, BIT(idx));
202203
}
203204

204-
static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx)
205+
static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx,
206+
struct cmdq_pkt *cmdq_pkt)
205207
{
206-
unsigned int reg;
207-
208-
reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
209-
reg = reg & ~BIT(idx);
210-
writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
211-
212-
writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
208+
mtk_ddp_write_mask(cmdq_pkt, 0, comp,
209+
DISP_REG_OVL_SRC_CON, BIT(idx));
210+
mtk_ddp_write(cmdq_pkt, 0, comp,
211+
DISP_REG_OVL_RDMA_CTRL(idx));
213212
}
214213

215214
static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
@@ -249,7 +248,8 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
249248
}
250249

251250
static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
252-
struct mtk_plane_state *state)
251+
struct mtk_plane_state *state,
252+
struct cmdq_pkt *cmdq_pkt)
253253
{
254254
struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
255255
struct mtk_plane_pending_state *pending = &state->pending;
@@ -261,7 +261,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
261261
unsigned int con;
262262

263263
if (!pending->enable)
264-
mtk_ovl_layer_off(comp, idx);
264+
mtk_ovl_layer_off(comp, idx, cmdq_pkt);
265265

266266
con = ovl_fmt_convert(ovl, fmt);
267267
if (idx != 0)
@@ -277,14 +277,19 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
277277
addr += pending->pitch - 1;
278278
}
279279

280-
writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx));
281-
writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx));
282-
writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx));
283-
writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx));
284-
writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(ovl, idx));
280+
mtk_ddp_write_relaxed(cmdq_pkt, con, comp,
281+
DISP_REG_OVL_CON(idx));
282+
mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp,
283+
DISP_REG_OVL_PITCH(idx));
284+
mtk_ddp_write_relaxed(cmdq_pkt, src_size, comp,
285+
DISP_REG_OVL_SRC_SIZE(idx));
286+
mtk_ddp_write_relaxed(cmdq_pkt, offset, comp,
287+
DISP_REG_OVL_OFFSET(idx));
288+
mtk_ddp_write_relaxed(cmdq_pkt, addr, comp,
289+
DISP_REG_OVL_ADDR(ovl, idx));
285290

286291
if (pending->enable)
287-
mtk_ovl_layer_on(comp, idx);
292+
mtk_ovl_layer_on(comp, idx, cmdq_pkt);
288293
}
289294

290295
static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp)

‎drivers/gpu/drm/mediatek/mtk_disp_rdma.c‎

Lines changed: 25 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#include <linux/of_device.h>
1010
#include <linux/of_irq.h>
1111
#include <linux/platform_device.h>
12+
#include <linux/soc/mediatek/mtk-cmdq.h>
1213

1314
#include "mtk_drm_crtc.h"
1415
#include "mtk_drm_ddp_comp.h"
@@ -125,14 +126,16 @@ static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
125126

126127
static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
127128
unsigned int height, unsigned int vrefresh,
128-
unsigned int bpc)
129+
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
129130
{
130131
unsigned int threshold;
131132
unsigned int reg;
132133
struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
133134

134-
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
135-
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
135+
mtk_ddp_write_mask(cmdq_pkt, width, comp,
136+
DISP_REG_RDMA_SIZE_CON_0, 0xfff);
137+
mtk_ddp_write_mask(cmdq_pkt, height, comp,
138+
DISP_REG_RDMA_SIZE_CON_1, 0xfffff);
136139

137140
/*
138141
* Enable FIFO underflow since DSI and DPI can't be blocked.
@@ -144,7 +147,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
144147
reg = RDMA_FIFO_UNDERFLOW_EN |
145148
RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) |
146149
RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
147-
writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
150+
mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON);
148151
}
149152

150153
static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
@@ -190,7 +193,8 @@ static unsigned int mtk_rdma_layer_nr(struct mtk_ddp_comp *comp)
190193
}
191194

192195
static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
193-
struct mtk_plane_state *state)
196+
struct mtk_plane_state *state,
197+
struct cmdq_pkt *cmdq_pkt)
194198
{
195199
struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
196200
struct mtk_plane_pending_state *pending = &state->pending;
@@ -200,24 +204,27 @@ static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
200204
unsigned int con;
201205

202206
con = rdma_fmt_convert(rdma, fmt);
203-
writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);
207+
mtk_ddp_write_relaxed(cmdq_pkt, con, comp, DISP_RDMA_MEM_CON);
204208

205209
if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {
206-
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
207-
RDMA_MATRIX_ENABLE, RDMA_MATRIX_ENABLE);
208-
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
209-
RDMA_MATRIX_INT_MTX_SEL,
210-
RDMA_MATRIX_INT_MTX_BT601_to_RGB);
210+
mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, comp,
211+
DISP_REG_RDMA_SIZE_CON_0,
212+
RDMA_MATRIX_ENABLE);
213+
mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,
214+
comp, DISP_REG_RDMA_SIZE_CON_0,
215+
RDMA_MATRIX_INT_MTX_SEL);
211216
} else {
212-
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
213-
RDMA_MATRIX_ENABLE, 0);
217+
mtk_ddp_write_mask(cmdq_pkt, 0, comp,
218+
DISP_REG_RDMA_SIZE_CON_0,
219+
RDMA_MATRIX_ENABLE);
214220
}
221+
mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, DISP_RDMA_MEM_START_ADDR);
222+
mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, DISP_RDMA_MEM_SRC_PITCH);
223+
mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, comp,
224+
DISP_RDMA_MEM_GMC_SETTING_0);
225+
mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, comp,
226+
DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY);
215227

216-
writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
217-
writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
218-
writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0);
219-
rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
220-
RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
221228
}
222229

223230
static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = {

‎drivers/gpu/drm/mediatek/mtk_drm_crtc.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -302,7 +302,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
302302
if (i == 1)
303303
mtk_ddp_comp_bgclr_in_on(comp);
304304

305-
mtk_ddp_comp_config(comp, width, height, vrefresh, bpc);
305+
mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
306306
mtk_ddp_comp_start(comp);
307307
}
308308

@@ -317,7 +317,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
317317
comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
318318
if (comp)
319319
mtk_ddp_comp_layer_config(comp, local_layer,
320-
plane_state);
320+
plane_state, NULL);
321321
}
322322

323323
return 0;
@@ -383,7 +383,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
383383
if (state->pending_config) {
384384
mtk_ddp_comp_config(comp, state->pending_width,
385385
state->pending_height,
386-
state->pending_vrefresh, 0);
386+
state->pending_vrefresh, 0, NULL);
387387

388388
state->pending_config = false;
389389
}
@@ -403,7 +403,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
403403

404404
if (comp)
405405
mtk_ddp_comp_layer_config(comp, local_layer,
406-
plane_state);
406+
plane_state, NULL);
407407
plane_state->pending.config = false;
408408
}
409409
mtk_crtc->pending_planes = false;
@@ -424,7 +424,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
424424

425425
if (comp)
426426
mtk_ddp_comp_layer_config(comp, local_layer,
427-
plane_state);
427+
plane_state, NULL);
428428
plane_state->pending.async_config = false;
429429
}
430430
mtk_crtc->pending_async_planes = false;

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