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Alex Elderdavem330
Alex Elder
authored and
davem330
committed
net: ipa: define IPA v3.1 GSI event ring register offsets
Add definitions of the offsets and strides for registers whose offset depends on an event ring ID, and use gsi_reg() and its returned value to determine offsets for these registers. Get rid of the corresponding GSI_EV_CH_E_*_OFFSET() macros. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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+90
-53
lines changed

3 files changed

+90
-53
lines changed

‎drivers/net/ipa/gsi.c‎

Lines changed: 32 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -392,9 +392,10 @@ static bool gsi_command(struct gsi *gsi, u32 reg, u32 val)
392392
static enum gsi_evt_ring_state
393393
gsi_evt_ring_state(struct gsi *gsi, u32 evt_ring_id)
394394
{
395+
const struct reg *reg = gsi_reg(gsi, EV_CH_E_CNTXT_0);
395396
u32 val;
396397

397-
val = ioread32(gsi->virt + GSI_EV_CH_E_CNTXT_0_OFFSET(evt_ring_id));
398+
val = ioread32(gsi->virt + reg_n_offset(reg, evt_ring_id));
398399

399400
return u32_get_bits(val, EV_CHSTATE_FMASK);
400401
}
@@ -690,56 +691,72 @@ static void gsi_channel_de_alloc_command(struct gsi *gsi, u32 channel_id)
690691
*/
691692
static void gsi_evt_ring_doorbell(struct gsi *gsi, u32 evt_ring_id, u32 index)
692693
{
694+
const struct reg *reg = gsi_reg(gsi, EV_CH_E_DOORBELL_0);
693695
struct gsi_ring *ring = &gsi->evt_ring[evt_ring_id].ring;
694696
u32 val;
695697

696698
ring->index = index; /* Next unused entry */
697699

698700
/* Note: index *must* be used modulo the ring count here */
699701
val = gsi_ring_addr(ring, (index - 1) % ring->count);
700-
iowrite32(val, gsi->virt + GSI_EV_CH_E_DOORBELL_0_OFFSET(evt_ring_id));
702+
iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id));
701703
}
702704

703705
/* Program an event ring for use */
704706
static void gsi_evt_ring_program(struct gsi *gsi, u32 evt_ring_id)
705707
{
706708
struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id];
707709
struct gsi_ring *ring = &evt_ring->ring;
710+
const struct reg *reg;
708711
size_t size;
709712
u32 val;
710713

714+
reg = gsi_reg(gsi, EV_CH_E_CNTXT_0);
711715
/* We program all event rings as GPI type/protocol */
712716
val = u32_encode_bits(GSI_CHANNEL_TYPE_GPI, EV_CHTYPE_FMASK);
713717
val |= EV_INTYPE_FMASK;
714718
val |= u32_encode_bits(GSI_RING_ELEMENT_SIZE, EV_ELEMENT_SIZE_FMASK);
715-
iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_0_OFFSET(evt_ring_id));
719+
iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id));
716720

721+
reg = gsi_reg(gsi, EV_CH_E_CNTXT_1);
717722
size = ring->count * GSI_RING_ELEMENT_SIZE;
718723
val = ev_ch_e_cntxt_1_length_encode(gsi->version, size);
719-
iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_1_OFFSET(evt_ring_id));
724+
iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id));
720725

721726
/* The context 2 and 3 registers store the low-order and
722727
* high-order 32 bits of the address of the event ring,
723728
* respectively.
724729
*/
730+
reg = gsi_reg(gsi, EV_CH_E_CNTXT_2);
725731
val = lower_32_bits(ring->addr);
726-
iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_2_OFFSET(evt_ring_id));
732+
iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id));
733+
734+
reg = gsi_reg(gsi, EV_CH_E_CNTXT_3);
727735
val = upper_32_bits(ring->addr);
728-
iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_3_OFFSET(evt_ring_id));
736+
iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id));
729737

730738
/* Enable interrupt moderation by setting the moderation delay */
739+
reg = gsi_reg(gsi, EV_CH_E_CNTXT_8);
731740
val = u32_encode_bits(GSI_EVT_RING_INT_MODT, MODT_FMASK);
732741
val |= u32_encode_bits(1, MODC_FMASK); /* comes from channel */
733-
iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_8_OFFSET(evt_ring_id));
742+
iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id));
734743

735744
/* No MSI write data, and MSI address high and low address is 0 */
736-
iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_9_OFFSET(evt_ring_id));
737-
iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_10_OFFSET(evt_ring_id));
738-
iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_11_OFFSET(evt_ring_id));
745+
reg = gsi_reg(gsi, EV_CH_E_CNTXT_9);
746+
iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id));
747+
748+
reg = gsi_reg(gsi, EV_CH_E_CNTXT_10);
749+
iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id));
750+
751+
reg = gsi_reg(gsi, EV_CH_E_CNTXT_11);
752+
iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id));
739753

740754
/* We don't need to get event read pointer updates */
741-
iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_12_OFFSET(evt_ring_id));
742-
iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_13_OFFSET(evt_ring_id));
755+
reg = gsi_reg(gsi, EV_CH_E_CNTXT_12);
756+
iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id));
757+
758+
reg = gsi_reg(gsi, EV_CH_E_CNTXT_13);
759+
iowrite32(0, gsi->virt + reg_n_offset(reg, evt_ring_id));
743760

744761
/* Finally, tell the hardware our "last processed" event (arbitrary) */
745762
gsi_evt_ring_doorbell(gsi, evt_ring_id, ring->index);
@@ -1538,6 +1555,7 @@ void gsi_channel_update(struct gsi_channel *channel)
15381555
struct gsi_evt_ring *evt_ring;
15391556
struct gsi_trans *trans;
15401557
struct gsi_ring *ring;
1558+
const struct reg *reg;
15411559
u32 offset;
15421560
u32 index;
15431561

@@ -1547,7 +1565,8 @@ void gsi_channel_update(struct gsi_channel *channel)
15471565
/* See if there's anything new to process; if not, we're done. Note
15481566
* that index always refers to an entry *within* the event ring.
15491567
*/
1550-
offset = GSI_EV_CH_E_CNTXT_4_OFFSET(evt_ring_id);
1568+
reg = gsi_reg(gsi, EV_CH_E_CNTXT_4);
1569+
offset = reg_n_offset(reg, evt_ring_id);
15511570
index = gsi_ring_index(ring, ioread32(gsi->virt + offset));
15521571
if (index == ring->index % ring->count)
15531572
return;

‎drivers/net/ipa/gsi_reg.h‎

Lines changed: 2 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -150,8 +150,7 @@ enum gsi_prefetch_mode {
150150
GSI_FREE_PREFETCH = 0x3,
151151
};
152152

153-
#define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \
154-
(0x0001d000 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
153+
/* EV_CH_E_CNTXT_0 register */
155154
/* enum gsi_channel_type defines EV_CHTYPE field values in EV_CH_E_CNTXT_0 */
156155
#define EV_CHTYPE_FMASK GENMASK(3, 0)
157156
#define EV_EE_FMASK GENMASK(7, 4)
@@ -160,48 +159,11 @@ enum gsi_prefetch_mode {
160159
#define EV_CHSTATE_FMASK GENMASK(23, 20)
161160
#define EV_ELEMENT_SIZE_FMASK GENMASK(31, 24)
162161

163-
#define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \
164-
(0x0001d004 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
165-
166-
#define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \
167-
(0x0001d008 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
168-
169-
#define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \
170-
(0x0001d00c + 0x4000 * GSI_EE_AP + 0x80 * (ev))
171-
172-
#define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \
173-
(0x0001d010 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
174-
175-
#define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \
176-
(0x0001d020 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
162+
/* EV_CH_E_CNTXT_8 register */
177163
#define MODT_FMASK GENMASK(15, 0)
178164
#define MODC_FMASK GENMASK(23, 16)
179165
#define MOD_CNT_FMASK GENMASK(31, 24)
180166

181-
#define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \
182-
(0x0001d024 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
183-
184-
#define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \
185-
(0x0001d028 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
186-
187-
#define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \
188-
(0x0001d02c + 0x4000 * GSI_EE_AP + 0x80 * (ev))
189-
190-
#define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \
191-
(0x0001d030 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
192-
193-
#define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \
194-
(0x0001d034 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
195-
196-
#define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \
197-
(0x0001d048 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
198-
199-
#define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \
200-
(0x0001d04c + 0x4000 * GSI_EE_AP + 0x80 * (ev))
201-
202-
#define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \
203-
(0x0001e100 + 0x4000 * GSI_EE_AP + 0x08 * (ev))
204-
205167
#define GSI_GSI_STATUS_OFFSET \
206168
(0x0001f000 + 0x4000 * GSI_EE_AP)
207169
#define ENABLED_FMASK GENMASK(0, 0)

‎drivers/net/ipa/reg/gsi_reg-v3.1.c‎

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,9 +30,51 @@ REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
3030
REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
3131
0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
3232

33+
REG_STRIDE(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
34+
0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);
35+
36+
REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
37+
0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);
38+
39+
REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
40+
0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);
41+
42+
REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
43+
0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);
44+
45+
REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
46+
0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);
47+
48+
REG_STRIDE(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
49+
0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);
50+
51+
REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
52+
0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);
53+
54+
REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
55+
0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);
56+
57+
REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
58+
0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);
59+
60+
REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
61+
0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);
62+
63+
REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
64+
0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);
65+
66+
REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
67+
0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);
68+
69+
REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
70+
0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);
71+
3372
REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
3473
0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
3574

75+
REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
76+
0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
77+
3678
static const struct reg *reg_array[] = {
3779
[CH_C_CNTXT_0] = &reg_ch_c_cntxt_0,
3880
[CH_C_CNTXT_1] = &reg_ch_c_cntxt_1,
@@ -43,7 +85,21 @@ static const struct reg *reg_array[] = {
4385
[CH_C_SCRATCH_1] = &reg_ch_c_scratch_1,
4486
[CH_C_SCRATCH_2] = &reg_ch_c_scratch_2,
4587
[CH_C_SCRATCH_3] = &reg_ch_c_scratch_3,
88+
[EV_CH_E_CNTXT_0] = &reg_ev_ch_e_cntxt_0,
89+
[EV_CH_E_CNTXT_1] = &reg_ev_ch_e_cntxt_1,
90+
[EV_CH_E_CNTXT_2] = &reg_ev_ch_e_cntxt_2,
91+
[EV_CH_E_CNTXT_3] = &reg_ev_ch_e_cntxt_3,
92+
[EV_CH_E_CNTXT_4] = &reg_ev_ch_e_cntxt_4,
93+
[EV_CH_E_CNTXT_8] = &reg_ev_ch_e_cntxt_8,
94+
[EV_CH_E_CNTXT_9] = &reg_ev_ch_e_cntxt_9,
95+
[EV_CH_E_CNTXT_10] = &reg_ev_ch_e_cntxt_10,
96+
[EV_CH_E_CNTXT_11] = &reg_ev_ch_e_cntxt_11,
97+
[EV_CH_E_CNTXT_12] = &reg_ev_ch_e_cntxt_12,
98+
[EV_CH_E_CNTXT_13] = &reg_ev_ch_e_cntxt_13,
99+
[EV_CH_E_SCRATCH_0] = &reg_ev_ch_e_scratch_0,
100+
[EV_CH_E_SCRATCH_1] = &reg_ev_ch_e_scratch_1,
46101
[CH_C_DOORBELL_0] = &reg_ch_c_doorbell_0,
102+
[EV_CH_E_DOORBELL_0] = &reg_ev_ch_e_doorbell_0,
47103
};
48104

49105
const struct regs gsi_regs_v3_1 = {

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