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bjorn-helgaasbjorn-helgaas
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Merge branch 'pci/controller/rockchip'
- Add struct rockchip_pcie_ep kernel-doc to fix warnings (Damien Le Moal) - Simplify clock and reset handling by using bulk interfaces (Anand Moon) - Pass typed rockchip_pcie (not void) pointer to rockchip_pcie_disable_clocks() (Anand Moon) - Return -ENOMEM, not success, when pci_epc_mem_alloc_addr() fails (Dan Carpenter) * pci/controller/rockchip: PCI: rockchip-ep: Fix error code in rockchip_pcie_ep_init_ob_mem() PCI: rockchip: Refactor rockchip_pcie_disable_clocks() signature PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function PCI: rockchip: Simplify clock handling by using clk_bulk*() functions PCI: rockchip: Add missing fields descriptions for struct rockchip_pcie_ep
2 parents a306f01 + 7ca2887 commit d3f0bec

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3 files changed

+65
-194
lines changed

3 files changed

+65
-194
lines changed

‎drivers/pci/controller/pcie-rockchip-ep.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,10 @@
4040
* @irq_pci_fn: the latest PCI function that has updated the mapping of
4141
* the MSI/INTX IRQ dedicated outbound region.
4242
* @irq_pending: bitmask of asserted INTX IRQs.
43+
* @perst_irq: IRQ used for the PERST# signal.
44+
* @perst_asserted: True if the PERST# signal was asserted.
45+
* @link_up: True if the PCI link is up.
46+
* @link_training: Work item to execute PCI link training.
4347
*/
4448
struct rockchip_pcie_ep {
4549
struct rockchip_pcie rockchip;
@@ -784,6 +788,7 @@ static int rockchip_pcie_ep_init_ob_mem(struct rockchip_pcie_ep *ep)
784788
SZ_1M);
785789
if (!ep->irq_cpu_addr) {
786790
dev_err(dev, "failed to reserve memory space for MSI\n");
791+
err = -ENOMEM;
787792
goto err_epc_mem_exit;
788793
}
789794

‎drivers/pci/controller/pcie-rockchip.c‎

Lines changed: 37 additions & 182 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
3030
struct platform_device *pdev = to_platform_device(dev);
3131
struct device_node *node = dev->of_node;
3232
struct resource *regs;
33-
int err;
33+
int err, i;
3434

3535
if (rockchip->is_rc) {
3636
regs = platform_get_resource_byname(pdev,
@@ -69,55 +69,23 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
6969
if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
7070
rockchip->link_gen = 2;
7171

72-
rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");
73-
if (IS_ERR(rockchip->core_rst)) {
74-
if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
75-
dev_err(dev, "missing core reset property in node\n");
76-
return PTR_ERR(rockchip->core_rst);
77-
}
78-
79-
rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");
80-
if (IS_ERR(rockchip->mgmt_rst)) {
81-
if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
82-
dev_err(dev, "missing mgmt reset property in node\n");
83-
return PTR_ERR(rockchip->mgmt_rst);
84-
}
85-
86-
rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,
87-
"mgmt-sticky");
88-
if (IS_ERR(rockchip->mgmt_sticky_rst)) {
89-
if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
90-
dev_err(dev, "missing mgmt-sticky reset property in node\n");
91-
return PTR_ERR(rockchip->mgmt_sticky_rst);
92-
}
72+
for (i = 0; i < ROCKCHIP_NUM_PM_RSTS; i++)
73+
rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i];
9374

94-
rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");
95-
if (IS_ERR(rockchip->pipe_rst)) {
96-
if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
97-
dev_err(dev, "missing pipe reset property in node\n");
98-
return PTR_ERR(rockchip->pipe_rst);
99-
}
100-
101-
rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");
102-
if (IS_ERR(rockchip->pm_rst)) {
103-
if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
104-
dev_err(dev, "missing pm reset property in node\n");
105-
return PTR_ERR(rockchip->pm_rst);
106-
}
75+
err = devm_reset_control_bulk_get_exclusive(dev,
76+
ROCKCHIP_NUM_PM_RSTS,
77+
rockchip->pm_rsts);
78+
if (err)
79+
return dev_err_probe(dev, err, "Cannot get the PM reset\n");
10780

108-
rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk");
109-
if (IS_ERR(rockchip->pclk_rst)) {
110-
if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
111-
dev_err(dev, "missing pclk reset property in node\n");
112-
return PTR_ERR(rockchip->pclk_rst);
113-
}
81+
for (i = 0; i < ROCKCHIP_NUM_CORE_RSTS; i++)
82+
rockchip->core_rsts[i].id = rockchip_pci_core_rsts[i];
11483

115-
rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk");
116-
if (IS_ERR(rockchip->aclk_rst)) {
117-
if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
118-
dev_err(dev, "missing aclk reset property in node\n");
119-
return PTR_ERR(rockchip->aclk_rst);
120-
}
84+
err = devm_reset_control_bulk_get_exclusive(dev,
85+
ROCKCHIP_NUM_CORE_RSTS,
86+
rockchip->core_rsts);
87+
if (err)
88+
return dev_err_probe(dev, err, "Cannot get the Core resets\n");
12189

12290
if (rockchip->is_rc)
12391
rockchip->perst_gpio = devm_gpiod_get_optional(dev, "ep",
@@ -129,29 +97,10 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
12997
return dev_err_probe(dev, PTR_ERR(rockchip->perst_gpio),
13098
"failed to get PERST# GPIO\n");
13199

132-
rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
133-
if (IS_ERR(rockchip->aclk_pcie)) {
134-
dev_err(dev, "aclk clock not found\n");
135-
return PTR_ERR(rockchip->aclk_pcie);
136-
}
137-
138-
rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
139-
if (IS_ERR(rockchip->aclk_perf_pcie)) {
140-
dev_err(dev, "aclk_perf clock not found\n");
141-
return PTR_ERR(rockchip->aclk_perf_pcie);
142-
}
143-
144-
rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
145-
if (IS_ERR(rockchip->hclk_pcie)) {
146-
dev_err(dev, "hclk clock not found\n");
147-
return PTR_ERR(rockchip->hclk_pcie);
148-
}
149-
150-
rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
151-
if (IS_ERR(rockchip->clk_pcie_pm)) {
152-
dev_err(dev, "pm clock not found\n");
153-
return PTR_ERR(rockchip->clk_pcie_pm);
154-
}
100+
rockchip->num_clks = devm_clk_bulk_get_all(dev, &rockchip->clks);
101+
if (rockchip->num_clks < 0)
102+
return dev_err_probe(dev, rockchip->num_clks,
103+
"failed to get clocks\n");
155104

156105
return 0;
157106
}
@@ -169,23 +118,10 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
169118
int err, i;
170119
u32 regs;
171120

172-
err = reset_control_assert(rockchip->aclk_rst);
173-
if (err) {
174-
dev_err(dev, "assert aclk_rst err %d\n", err);
175-
return err;
176-
}
177-
178-
err = reset_control_assert(rockchip->pclk_rst);
179-
if (err) {
180-
dev_err(dev, "assert pclk_rst err %d\n", err);
181-
return err;
182-
}
183-
184-
err = reset_control_assert(rockchip->pm_rst);
185-
if (err) {
186-
dev_err(dev, "assert pm_rst err %d\n", err);
187-
return err;
188-
}
121+
err = reset_control_bulk_assert(ROCKCHIP_NUM_PM_RSTS,
122+
rockchip->pm_rsts);
123+
if (err)
124+
return dev_err_probe(dev, err, "Couldn't assert PM resets\n");
189125

190126
for (i = 0; i < MAX_LANE_NUM; i++) {
191127
err = phy_init(rockchip->phys[i]);
@@ -195,47 +131,19 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
195131
}
196132
}
197133

198-
err = reset_control_assert(rockchip->core_rst);
199-
if (err) {
200-
dev_err(dev, "assert core_rst err %d\n", err);
201-
goto err_exit_phy;
202-
}
203-
204-
err = reset_control_assert(rockchip->mgmt_rst);
205-
if (err) {
206-
dev_err(dev, "assert mgmt_rst err %d\n", err);
207-
goto err_exit_phy;
208-
}
209-
210-
err = reset_control_assert(rockchip->mgmt_sticky_rst);
211-
if (err) {
212-
dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
213-
goto err_exit_phy;
214-
}
215-
216-
err = reset_control_assert(rockchip->pipe_rst);
134+
err = reset_control_bulk_assert(ROCKCHIP_NUM_CORE_RSTS,
135+
rockchip->core_rsts);
217136
if (err) {
218-
dev_err(dev, "assert pipe_rst err %d\n", err);
137+
dev_err_probe(dev, err, "Couldn't assert Core resets\n");
219138
goto err_exit_phy;
220139
}
221140

222141
udelay(10);
223142

224-
err = reset_control_deassert(rockchip->pm_rst);
225-
if (err) {
226-
dev_err(dev, "deassert pm_rst err %d\n", err);
227-
goto err_exit_phy;
228-
}
229-
230-
err = reset_control_deassert(rockchip->aclk_rst);
231-
if (err) {
232-
dev_err(dev, "deassert aclk_rst err %d\n", err);
233-
goto err_exit_phy;
234-
}
235-
236-
err = reset_control_deassert(rockchip->pclk_rst);
143+
err = reset_control_bulk_deassert(ROCKCHIP_NUM_PM_RSTS,
144+
rockchip->pm_rsts);
237145
if (err) {
238-
dev_err(dev, "deassert pclk_rst err %d\n", err);
146+
dev_err(dev, "Couldn't deassert PM resets %d\n", err);
239147
goto err_exit_phy;
240148
}
241149

@@ -275,31 +183,10 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
275183
goto err_power_off_phy;
276184
}
277185

278-
/*
279-
* Please don't reorder the deassert sequence of the following
280-
* four reset pins.
281-
*/
282-
err = reset_control_deassert(rockchip->mgmt_sticky_rst);
283-
if (err) {
284-
dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
285-
goto err_power_off_phy;
286-
}
287-
288-
err = reset_control_deassert(rockchip->core_rst);
289-
if (err) {
290-
dev_err(dev, "deassert core_rst err %d\n", err);
291-
goto err_power_off_phy;
292-
}
293-
294-
err = reset_control_deassert(rockchip->mgmt_rst);
295-
if (err) {
296-
dev_err(dev, "deassert mgmt_rst err %d\n", err);
297-
goto err_power_off_phy;
298-
}
299-
300-
err = reset_control_deassert(rockchip->pipe_rst);
186+
err = reset_control_bulk_deassert(ROCKCHIP_NUM_CORE_RSTS,
187+
rockchip->core_rsts);
301188
if (err) {
302-
dev_err(dev, "deassert pipe_rst err %d\n", err);
189+
dev_err(dev, "Couldn't deassert Core reset %d\n", err);
303190
goto err_power_off_phy;
304191
}
305192

@@ -375,50 +262,18 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip)
375262
struct device *dev = rockchip->dev;
376263
int err;
377264

378-
err = clk_prepare_enable(rockchip->aclk_pcie);
379-
if (err) {
380-
dev_err(dev, "unable to enable aclk_pcie clock\n");
381-
return err;
382-
}
383-
384-
err = clk_prepare_enable(rockchip->aclk_perf_pcie);
385-
if (err) {
386-
dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
387-
goto err_aclk_perf_pcie;
388-
}
389-
390-
err = clk_prepare_enable(rockchip->hclk_pcie);
391-
if (err) {
392-
dev_err(dev, "unable to enable hclk_pcie clock\n");
393-
goto err_hclk_pcie;
394-
}
395-
396-
err = clk_prepare_enable(rockchip->clk_pcie_pm);
397-
if (err) {
398-
dev_err(dev, "unable to enable clk_pcie_pm clock\n");
399-
goto err_clk_pcie_pm;
400-
}
265+
err = clk_bulk_prepare_enable(rockchip->num_clks, rockchip->clks);
266+
if (err)
267+
return dev_err_probe(dev, err, "failed to enable clocks\n");
401268

402269
return 0;
403-
404-
err_clk_pcie_pm:
405-
clk_disable_unprepare(rockchip->hclk_pcie);
406-
err_hclk_pcie:
407-
clk_disable_unprepare(rockchip->aclk_perf_pcie);
408-
err_aclk_perf_pcie:
409-
clk_disable_unprepare(rockchip->aclk_pcie);
410-
return err;
411270
}
412271
EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks);
413272

414-
void rockchip_pcie_disable_clocks(void *data)
273+
void rockchip_pcie_disable_clocks(struct rockchip_pcie *rockchip)
415274
{
416-
struct rockchip_pcie *rockchip = data;
417275

418-
clk_disable_unprepare(rockchip->clk_pcie_pm);
419-
clk_disable_unprepare(rockchip->hclk_pcie);
420-
clk_disable_unprepare(rockchip->aclk_perf_pcie);
421-
clk_disable_unprepare(rockchip->aclk_pcie);
276+
clk_bulk_disable_unprepare(rockchip->num_clks, rockchip->clks);
422277
}
423278
EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks);
424279

‎drivers/pci/controller/pcie-rockchip.h‎

Lines changed: 23 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,11 @@
1111
#ifndef _PCIE_ROCKCHIP_H
1212
#define _PCIE_ROCKCHIP_H
1313

14+
#include <linux/clk.h>
1415
#include <linux/kernel.h>
1516
#include <linux/pci.h>
1617
#include <linux/pci-ecam.h>
18+
#include <linux/reset.h>
1719

1820
/*
1921
* The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
@@ -309,22 +311,31 @@
309311
(((c) << ((b) * 8 + 5)) & \
310312
ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
311313

314+
#define ROCKCHIP_NUM_PM_RSTS ARRAY_SIZE(rockchip_pci_pm_rsts)
315+
#define ROCKCHIP_NUM_CORE_RSTS ARRAY_SIZE(rockchip_pci_core_rsts)
316+
317+
static const char * const rockchip_pci_pm_rsts[] = {
318+
"pm",
319+
"pclk",
320+
"aclk",
321+
};
322+
323+
static const char * const rockchip_pci_core_rsts[] = {
324+
"mgmt-sticky",
325+
"core",
326+
"mgmt",
327+
"pipe",
328+
};
329+
312330
struct rockchip_pcie {
313331
void __iomem *reg_base; /* DT axi-base */
314332
void __iomem *apb_base; /* DT apb-base */
315333
bool legacy_phy;
316334
struct phy *phys[MAX_LANE_NUM];
317-
struct reset_control *core_rst;
318-
struct reset_control *mgmt_rst;
319-
struct reset_control *mgmt_sticky_rst;
320-
struct reset_control *pipe_rst;
321-
struct reset_control *pm_rst;
322-
struct reset_control *aclk_rst;
323-
struct reset_control *pclk_rst;
324-
struct clk *aclk_pcie;
325-
struct clk *aclk_perf_pcie;
326-
struct clk *hclk_pcie;
327-
struct clk *clk_pcie_pm;
335+
struct reset_control_bulk_data pm_rsts[ROCKCHIP_NUM_PM_RSTS];
336+
struct reset_control_bulk_data core_rsts[ROCKCHIP_NUM_CORE_RSTS];
337+
struct clk_bulk_data *clks;
338+
int num_clks;
328339
struct regulator *vpcie12v; /* 12V power supply */
329340
struct regulator *vpcie3v3; /* 3.3V power supply */
330341
struct regulator *vpcie1v8; /* 1.8V power supply */
@@ -358,7 +369,7 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip);
358369
int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip);
359370
void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip);
360371
int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip);
361-
void rockchip_pcie_disable_clocks(void *data);
372+
void rockchip_pcie_disable_clocks(struct rockchip_pcie *rockchip);
362373
void rockchip_pcie_cfg_configuration_accesses(
363374
struct rockchip_pcie *rockchip, u32 type);
364375

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