@@ -32,13 +32,6 @@ static const u32 ar9485_1_1_mac_postamble[][5] = {
3232 {0x00008318 , 0x00003e80 , 0x00007d00 , 0x00006880 , 0x00003440 },
3333};
3434
35- static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1 [][2 ] = {
36- /* Addr allmodes */
37- {0x00018c00 , 0x18012e5e },
38- {0x00018c04 , 0x000801d8 },
39- {0x00018c08 , 0x0000080c },
40- };
41-
4235static const u32 ar9485Common_wo_xlna_rx_gain_1_1 [][2 ] = {
4336 /* Addr allmodes */
4437 {0x00009e00 , 0x037216a0 },
@@ -1101,20 +1094,6 @@ static const u32 ar9485_common_rx_gain_1_1[][2] = {
11011094 {0x0000a1fc , 0x00000296 },
11021095};
11031096
1104- static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1 [][2 ] = {
1105- /* Addr allmodes */
1106- {0x00018c00 , 0x18052e5e },
1107- {0x00018c04 , 0x000801d8 },
1108- {0x00018c08 , 0x0000080c },
1109- };
1110-
1111- static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1 [][2 ] = {
1112- /* Addr allmodes */
1113- {0x00018c00 , 0x18053e5e },
1114- {0x00018c04 , 0x000801d8 },
1115- {0x00018c08 , 0x0000080c },
1116- };
1117-
11181097static const u32 ar9485_1_1_soc_preamble [][2 ] = {
11191098 /* Addr allmodes */
11201099 {0x00004014 , 0xba280400 },
@@ -1173,13 +1152,6 @@ static const u32 ar9485_1_1_baseband_postamble[][5] = {
11731152 {0x0000be18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 },
11741153};
11751154
1176- static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1 [][2 ] = {
1177- /* Addr allmodes */
1178- {0x00018c00 , 0x18013e5e },
1179- {0x00018c04 , 0x000801d8 },
1180- {0x00018c08 , 0x0000080c },
1181- };
1182-
11831155static const u32 ar9485_1_1_radio_postamble [][2 ] = {
11841156 /* Addr allmodes */
11851157 {0x0001609c , 0x0b283f31 },
@@ -1358,4 +1330,18 @@ static const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = {
13581330 {0x0000a3a0 , 0xca9228ee },
13591331};
13601332
1333+ static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1 [][2 ] = {
1334+ /* Addr allmodes */
1335+ {0x00018c00 , 0x18013e5e },
1336+ {0x00018c04 , 0x000801d8 },
1337+ {0x00018c08 , 0x0000080c },
1338+ };
1339+
1340+ static const u32 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1 [][2 ] = {
1341+ /* Addr allmodes */
1342+ {0x00018c00 , 0x1801265e },
1343+ {0x00018c04 , 0x000801d8 },
1344+ {0x00018c08 , 0x0000080c },
1345+ };
1346+
13611347#endif /* INITVALS_9485_H */
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