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2 parents bcfd5f6 + 9f3de72 commit dce210aCopy full SHA for dce210a
arch/x86/events/intel/core.c
@@ -7135,6 +7135,7 @@ __init int intel_pmu_init(void)
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case INTEL_METEORLAKE:
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case INTEL_METEORLAKE_L:
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+ case INTEL_ARROWLAKE_U:
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intel_pmu_init_hybrid(hybrid_big_small);
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x86_pmu.pebs_latency_data = cmt_latency_data;
arch/x86/events/intel/ds.c
@@ -1489,7 +1489,7 @@ void intel_pmu_pebs_enable(struct perf_event *event)
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* hence we need to drain when changing said
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* size.
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*/
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- intel_pmu_drain_large_pebs(cpuc);
+ intel_pmu_drain_pebs_buffer();
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adaptive_pebs_record_size_update();
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wrmsrl(MSR_PEBS_DATA_CFG, pebs_data_cfg);
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cpuc->active_pebs_data_cfg = pebs_data_cfg;
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