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Jeff Garzikjejb
Jeff Garzik
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jejb
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[SCSI] mvsas: split driver into multiple files
Split mvsas driver into multiple source codes, based on the split and function distribution found in Marvell's mvsas update. Signed-off-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
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‎drivers/scsi/mvsas/Makefile‎

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# USA
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obj-$(CONFIG_SCSI_MVSAS) += mvsas.o
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mvsas-y += mv_sas.o
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mvsas-y += mv_init.o \
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mv_sas.o \
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mv_64xx.o

‎drivers/scsi/mvsas/mv_64xx.c‎

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/*
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mv_64xx.c - Marvell 88SE6440 SAS/SATA support
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Copyright 2007 Red Hat, Inc.
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Copyright 2008 Marvell. <kewei@marvell.com>
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2,
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or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty
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of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public
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License along with this program; see the file COPYING. If not,
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write to the Free Software Foundation, 675 Mass Ave, Cambridge,
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MA 02139, USA.
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*/
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#include "mv_sas.h"
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#include "mv_64xx.h"
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#include "mv_chips.h"
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void mvs_detect_porttype(struct mvs_info *mvi, int i)
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{
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void __iomem *regs = mvi->regs;
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u32 reg;
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struct mvs_phy *phy = &mvi->phy[i];
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/* TODO check & save device type */
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reg = mr32(GBL_PORT_TYPE);
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if (reg & MODE_SAS_SATA & (1 << i))
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phy->phy_type |= PORT_TYPE_SAS;
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else
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phy->phy_type |= PORT_TYPE_SATA;
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}
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void mvs_enable_xmt(struct mvs_info *mvi, int PhyId)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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tmp = mr32(PCS);
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if (mvi->chip->n_phy <= 4)
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tmp |= 1 << (PhyId + PCS_EN_PORT_XMT_SHIFT);
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else
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tmp |= 1 << (PhyId + PCS_EN_PORT_XMT_SHIFT2);
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mw32(PCS, tmp);
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}
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void __devinit mvs_phy_hacks(struct mvs_info *mvi)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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/* workaround for SATA R-ERR, to ignore phy glitch */
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tmp = mvs_cr32(regs, CMD_PHY_TIMER);
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tmp &= ~(1 << 9);
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tmp |= (1 << 10);
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mvs_cw32(regs, CMD_PHY_TIMER, tmp);
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/* enable retry 127 times */
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mvs_cw32(regs, CMD_SAS_CTL1, 0x7f7f);
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/* extend open frame timeout to max */
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tmp = mvs_cr32(regs, CMD_SAS_CTL0);
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tmp &= ~0xffff;
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tmp |= 0x3fff;
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mvs_cw32(regs, CMD_SAS_CTL0, tmp);
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/* workaround for WDTIMEOUT , set to 550 ms */
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mvs_cw32(regs, CMD_WD_TIMER, 0x86470);
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/* not to halt for different port op during wideport link change */
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mvs_cw32(regs, CMD_APP_ERR_CONFIG, 0xffefbf7d);
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/* workaround for Seagate disk not-found OOB sequence, recv
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* COMINIT before sending out COMWAKE */
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tmp = mvs_cr32(regs, CMD_PHY_MODE_21);
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tmp &= 0x0000ffff;
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tmp |= 0x00fa0000;
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mvs_cw32(regs, CMD_PHY_MODE_21, tmp);
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tmp = mvs_cr32(regs, CMD_PHY_TIMER);
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tmp &= 0x1fffffff;
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tmp |= (2U << 29); /* 8 ms retry */
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mvs_cw32(regs, CMD_PHY_TIMER, tmp);
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/* TEST - for phy decoding error, adjust voltage levels */
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mw32(P0_VSR_ADDR + 0, 0x8);
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mw32(P0_VSR_DATA + 0, 0x2F0);
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mw32(P0_VSR_ADDR + 8, 0x8);
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mw32(P0_VSR_DATA + 8, 0x2F0);
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mw32(P0_VSR_ADDR + 16, 0x8);
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mw32(P0_VSR_DATA + 16, 0x2F0);
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mw32(P0_VSR_ADDR + 24, 0x8);
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mw32(P0_VSR_DATA + 24, 0x2F0);
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}
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void mvs_hba_interrupt_enable(struct mvs_info *mvi)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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tmp = mr32(GBL_CTL);
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mw32(GBL_CTL, tmp | INT_EN);
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}
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void mvs_hba_interrupt_disable(struct mvs_info *mvi)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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tmp = mr32(GBL_CTL);
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mw32(GBL_CTL, tmp & ~INT_EN);
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}
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void mvs_free_reg_set(struct mvs_info *mvi, struct mvs_port *port)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp, offs;
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u8 *tfs = &port->taskfileset;
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if (*tfs == MVS_ID_NOT_MAPPED)
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return;
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offs = 1U << ((*tfs & 0x0f) + PCS_EN_SATA_REG_SHIFT);
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if (*tfs < 16) {
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tmp = mr32(PCS);
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mw32(PCS, tmp & ~offs);
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} else {
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tmp = mr32(CTL);
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mw32(CTL, tmp & ~offs);
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}
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tmp = mr32(INT_STAT_SRS) & (1U << *tfs);
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if (tmp)
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mw32(INT_STAT_SRS, tmp);
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*tfs = MVS_ID_NOT_MAPPED;
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}
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u8 mvs_assign_reg_set(struct mvs_info *mvi, struct mvs_port *port)
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{
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int i;
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u32 tmp, offs;
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void __iomem *regs = mvi->regs;
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if (port->taskfileset != MVS_ID_NOT_MAPPED)
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return 0;
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tmp = mr32(PCS);
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for (i = 0; i < mvi->chip->srs_sz; i++) {
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if (i == 16)
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tmp = mr32(CTL);
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offs = 1U << ((i & 0x0f) + PCS_EN_SATA_REG_SHIFT);
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if (!(tmp & offs)) {
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port->taskfileset = i;
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if (i < 16)
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mw32(PCS, tmp | offs);
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else
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mw32(CTL, tmp | offs);
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tmp = mr32(INT_STAT_SRS) & (1U << i);
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if (tmp)
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mw32(INT_STAT_SRS, tmp);
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return 0;
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}
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}
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return MVS_ID_NOT_MAPPED;
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}
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‎drivers/scsi/mvsas/mv_64xx.h‎

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#ifndef _MVS64XX_REG_H_
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#define _MVS64XX_REG_H_
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/* enhanced mode registers (BAR4) */
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enum hw_registers {
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MVS_GBL_CTL = 0x04, /* global control */
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MVS_GBL_INT_STAT = 0x08, /* global irq status */
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MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
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MVS_GBL_PORT_TYPE = 0xa0, /* port type */
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MVS_CTL = 0x100, /* SAS/SATA port configuration */
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MVS_PCS = 0x104, /* SAS/SATA port control/status */
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MVS_CMD_LIST_LO = 0x108, /* cmd list addr */
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MVS_CMD_LIST_HI = 0x10C,
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MVS_RX_FIS_LO = 0x110, /* RX FIS list addr */
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MVS_RX_FIS_HI = 0x114,
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MVS_TX_CFG = 0x120, /* TX configuration */
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MVS_TX_LO = 0x124, /* TX (delivery) ring addr */
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MVS_TX_HI = 0x128,
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MVS_TX_PROD_IDX = 0x12C, /* TX producer pointer */
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MVS_TX_CONS_IDX = 0x130, /* TX consumer pointer (RO) */
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MVS_RX_CFG = 0x134, /* RX configuration */
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MVS_RX_LO = 0x138, /* RX (completion) ring addr */
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MVS_RX_HI = 0x13C,
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MVS_RX_CONS_IDX = 0x140, /* RX consumer pointer (RO) */
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MVS_INT_COAL = 0x148, /* Int coalescing config */
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MVS_INT_COAL_TMOUT = 0x14C, /* Int coalescing timeout */
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MVS_INT_STAT = 0x150, /* Central int status */
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MVS_INT_MASK = 0x154, /* Central int enable */
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MVS_INT_STAT_SRS = 0x158, /* SATA register set status */
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MVS_INT_MASK_SRS = 0x15C,
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/* ports 1-3 follow after this */
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MVS_P0_INT_STAT = 0x160, /* port0 interrupt status */
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MVS_P0_INT_MASK = 0x164, /* port0 interrupt mask */
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MVS_P4_INT_STAT = 0x200, /* Port 4 interrupt status */
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MVS_P4_INT_MASK = 0x204, /* Port 4 interrupt enable mask */
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/* ports 1-3 follow after this */
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MVS_P0_SER_CTLSTAT = 0x180, /* port0 serial control/status */
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MVS_P4_SER_CTLSTAT = 0x220, /* port4 serial control/status */
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MVS_CMD_ADDR = 0x1B8, /* Command register port (addr) */
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MVS_CMD_DATA = 0x1BC, /* Command register port (data) */
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/* ports 1-3 follow after this */
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MVS_P0_CFG_ADDR = 0x1C0, /* port0 phy register address */
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MVS_P0_CFG_DATA = 0x1C4, /* port0 phy register data */
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MVS_P4_CFG_ADDR = 0x230, /* Port 4 config address */
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MVS_P4_CFG_DATA = 0x234, /* Port 4 config data */
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/* ports 1-3 follow after this */
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MVS_P0_VSR_ADDR = 0x1E0, /* port0 VSR address */
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MVS_P0_VSR_DATA = 0x1E4, /* port0 VSR data */
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MVS_P4_VSR_ADDR = 0x250, /* port 4 VSR addr */
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MVS_P4_VSR_DATA = 0x254, /* port 4 VSR data */
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};
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enum pci_cfg_registers {
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PCR_PHY_CTL = 0x40,
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PCR_PHY_CTL2 = 0x90,
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PCR_DEV_CTRL = 0xE8,
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};
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/* SAS/SATA Vendor Specific Port Registers */
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enum sas_sata_vsp_regs {
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VSR_PHY_STAT = 0x00, /* Phy Status */
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VSR_PHY_MODE1 = 0x01, /* phy tx */
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VSR_PHY_MODE2 = 0x02, /* tx scc */
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VSR_PHY_MODE3 = 0x03, /* pll */
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VSR_PHY_MODE4 = 0x04, /* VCO */
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VSR_PHY_MODE5 = 0x05, /* Rx */
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VSR_PHY_MODE6 = 0x06, /* CDR */
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VSR_PHY_MODE7 = 0x07, /* Impedance */
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VSR_PHY_MODE8 = 0x08, /* Voltage */
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VSR_PHY_MODE9 = 0x09, /* Test */
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VSR_PHY_MODE10 = 0x0A, /* Power */
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VSR_PHY_MODE11 = 0x0B, /* Phy Mode */
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VSR_PHY_VS0 = 0x0C, /* Vednor Specific 0 */
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VSR_PHY_VS1 = 0x0D, /* Vednor Specific 1 */
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};
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struct mvs_prd {
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__le64 addr; /* 64-bit buffer address */
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__le32 reserved;
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__le32 len; /* 16-bit length */
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};
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#endif

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