Revert "Merge: EDAC: add initial support for El Capitan"

This reverts commit 7315692, reversing
changes made to 66f48ff.

Before we merge this up to 9.5, let's wait for [1] to be merged to avoid
needing to rebase that MR.

[1] https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-9/-/merge_requests/3680

Signed-off-by: Scott Weaver <scweaver@redhat.com>

Author: swvrrh

Documentation/driver-api/edac.rst

@@ -106,16 +106,6 @@ will occupy those chip-select rows.
 This term is avoided because it is unclear when needing to distinguish
 between chip-select rows and socket sets.
 
-* High Bandwidth Memory (HBM)
-
-HBM is a new memory type with low power consumption and ultra-wide
-communication lanes. It uses vertically stacked memory chips (DRAM dies)
-interconnected by microscopic wires called "through-silicon vias," or
-TSVs.
-
-Several stacks of HBM chips connect to the CPU or GPU through an ultra-fast
-interconnect called the "interposer". Therefore, HBM's characteristics
-are nearly indistinguishable from on-chip integrated RAM.
 
 Memory Controllers
 ------------------
@@ -186,113 +176,3 @@ nodes::
 	the L1 and L2 directories would be "edac_device_block's"
 
 .. kernel-doc:: drivers/edac/edac_device.h
-
-
-Heterogeneous system support
-----------------------------
-
-An AMD heterogeneous system is built by connecting the data fabrics of
-both CPUs and GPUs via custom xGMI links. Thus, the data fabric on the
-GPU nodes can be accessed the same way as the data fabric on CPU nodes.
-
-The MI200 accelerators are data center GPUs. They have 2 data fabrics,
-and each GPU data fabric contains four Unified Memory Controllers (UMC).
-Each UMC contains eight channels. Each UMC channel controls one 128-bit
-HBM2e (2GB) channel (equivalent to 8 X 2GB ranks).  This creates a total
-of 4096-bits of DRAM data bus.
-
-While the UMC is interfacing a 16GB (8high X 2GB DRAM) HBM stack, each UMC
-channel is interfacing 2GB of DRAM (represented as rank).
-
-Memory controllers on AMD GPU nodes can be represented in EDAC thusly:
-
-	GPU DF / GPU Node -> EDAC MC
-	GPU UMC           -> EDAC CSROW
-	GPU UMC channel   -> EDAC CHANNEL
-
-For example: a heterogeneous system with 1 AMD CPU is connected to
-4 MI200 (Aldebaran) GPUs using xGMI.
-
-Some more heterogeneous hardware details:
-
-- The CPU UMC (Unified Memory Controller) is mostly the same as the GPU UMC.
-  They have chip selects (csrows) and channels. However, the layouts are different
-  for performance, physical layout, or other reasons.
-- CPU UMCs use 1 channel, In this case UMC = EDAC channel. This follows the
-  marketing speak. CPU has X memory channels, etc.
-- CPU UMCs use up to 4 chip selects, So UMC chip select = EDAC CSROW.
-- GPU UMCs use 1 chip select, So UMC = EDAC CSROW.
-- GPU UMCs use 8 channels, So UMC channel = EDAC channel.
-
-The EDAC subsystem provides a mechanism to handle AMD heterogeneous
-systems by calling system specific ops for both CPUs and GPUs.
-
-AMD GPU nodes are enumerated in sequential order based on the PCI
-hierarchy, and the first GPU node is assumed to have a Node ID value
-following those of the CPU nodes after latter are fully populated::
-
-	$ ls /sys/devices/system/edac/mc/
-		mc0   - CPU MC node 0
-		mc1  |
-		mc2  |- GPU card[0] => node 0(mc1), node 1(mc2)
-		mc3  |
-		mc4  |- GPU card[1] => node 0(mc3), node 1(mc4)
-		mc5  |
-		mc6  |- GPU card[2] => node 0(mc5), node 1(mc6)
-		mc7  |
-		mc8  |- GPU card[3] => node 0(mc7), node 1(mc8)
-
-For example, a heterogeneous system with one AMD CPU is connected to
-four MI200 (Aldebaran) GPUs using xGMI. This topology can be represented
-via the following sysfs entries::
-
-	/sys/devices/system/edac/mc/..
-
-	CPU			# CPU node
-	├── mc 0
-
-	GPU Nodes are enumerated sequentially after CPU nodes have been populated
-	GPU card 1		# Each MI200 GPU has 2 nodes/mcs
-	├── mc 1		# GPU node 0 == mc1, Each MC node has 4 UMCs/CSROWs
-	│   ├── csrow 0		# UMC 0
-	│   │   ├── channel 0	# Each UMC has 8 channels
-	│   │   ├── channel 1   # size of each channel is 2 GB, so each UMC has 16 GB
-	│   │   ├── channel 2
-	│   │   ├── channel 3
-	│   │   ├── channel 4
-	│   │   ├── channel 5
-	│   │   ├── channel 6
-	│   │   ├── channel 7
-	│   ├── csrow 1		# UMC 1
-	│   │   ├── channel 0
-	│   │   ├── ..
-	│   │   ├── channel 7
-	│   ├── ..		..
-	│   ├── csrow 3		# UMC 3
-	│   │   ├── channel 0
-	│   │   ├── ..
-	│   │   ├── channel 7
-	│   ├── rank 0
-	│   ├── ..		..
-	│   ├── rank 31		# total 32 ranks/dimms from 4 UMCs
-	├
-	├── mc 2		# GPU node 1 == mc2
-	│   ├── ..		# each GPU has total 64 GB
-
-	GPU card 2
-	├── mc 3
-	│   ├── ..
-	├── mc 4
-	│   ├── ..
-
-	GPU card 3
-	├── mc 5
-	│   ├── ..
-	├── mc 6
-	│   ├── ..
-
-	GPU card 4
-	├── mc 7
-	│   ├── ..
-	├── mc 8
-	│   ├── ..

arch/x86/include/asm/mce.h

@@ -307,7 +307,6 @@ enum smca_bank_types {
 	SMCA_PIE,	/* Power, Interrupts, etc. */
 	SMCA_UMC,	/* Unified Memory Controller */
 	SMCA_UMC_V2,
-	SMCA_MA_LLC,	/* Memory Attached Last Level Cache */
 	SMCA_PB,	/* Parameter Block */
 	SMCA_PSP,	/* Platform Security Processor */
 	SMCA_PSP_V2,
@@ -323,15 +322,14 @@ enum smca_bank_types {
 	SMCA_SHUB,	/* System HUB Unit */
 	SMCA_SATA,	/* SATA Unit */
 	SMCA_USB,	/* USB Unit */
-	SMCA_USR_DP,	/* Ultra Short Reach Data Plane Controller */
-	SMCA_USR_CP,	/* Ultra Short Reach Control Plane Controller */
 	SMCA_GMI_PCS,	/* GMI PCS Unit */
 	SMCA_XGMI_PHY,	/* xGMI PHY Unit */
 	SMCA_WAFL_PHY,	/* WAFL PHY Unit */
 	SMCA_GMI_PHY,	/* GMI PHY Unit */
 	N_SMCA_BANK_TYPES
 };
 
+extern const char *smca_get_long_name(enum smca_bank_types t);
 extern bool amd_mce_is_memory_error(struct mce *m);
 
 extern int mce_threshold_create_device(unsigned int cpu);

arch/x86/kernel/cpu/mce/amd.c

@@ -87,50 +87,61 @@ struct smca_bank {
 static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks);
 static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts);
 
-static const char * const smca_names[] = {
-	[SMCA_LS ... SMCA_LS_V2]	= "load_store",
-	[SMCA_IF]			= "insn_fetch",
-	[SMCA_L2_CACHE]			= "l2_cache",
-	[SMCA_DE]			= "decode_unit",
-	[SMCA_RESERVED]			= "reserved",
-	[SMCA_EX]			= "execution_unit",
-	[SMCA_FP]			= "floating_point",
-	[SMCA_L3_CACHE]			= "l3_cache",
-	[SMCA_CS ... SMCA_CS_V2]	= "coherent_slave",
-	[SMCA_PIE]			= "pie",
+struct smca_bank_name {
+	const char *name;	/* Short name for sysfs */
+	const char *long_name;	/* Long name for pretty-printing */
+};
+
+static struct smca_bank_name smca_names[] = {
+	[SMCA_LS ... SMCA_LS_V2]	= { "load_store",	"Load Store Unit" },
+	[SMCA_IF]			= { "insn_fetch",	"Instruction Fetch Unit" },
+	[SMCA_L2_CACHE]			= { "l2_cache",		"L2 Cache" },
+	[SMCA_DE]			= { "decode_unit",	"Decode Unit" },
+	[SMCA_RESERVED]			= { "reserved",		"Reserved" },
+	[SMCA_EX]			= { "execution_unit",	"Execution Unit" },
+	[SMCA_FP]			= { "floating_point",	"Floating Point Unit" },
+	[SMCA_L3_CACHE]			= { "l3_cache",		"L3 Cache" },
+	[SMCA_CS ... SMCA_CS_V2]	= { "coherent_slave",	"Coherent Slave" },
+	[SMCA_PIE]			= { "pie",		"Power, Interrupts, etc." },
 
 	/* UMC v2 is separate because both of them can exist in a single system. */
-	[SMCA_UMC]			= "umc",
-	[SMCA_UMC_V2]			= "umc_v2",
-	[SMCA_MA_LLC]			= "ma_llc",
-	[SMCA_PB]			= "param_block",
-	[SMCA_PSP ... SMCA_PSP_V2]	= "psp",
-	[SMCA_SMU ... SMCA_SMU_V2]	= "smu",
-	[SMCA_MP5]			= "mp5",
-	[SMCA_MPDMA]			= "mpdma",
-	[SMCA_NBIO]			= "nbio",
-	[SMCA_PCIE ... SMCA_PCIE_V2]	= "pcie",
-	[SMCA_XGMI_PCS]			= "xgmi_pcs",
-	[SMCA_NBIF]			= "nbif",
-	[SMCA_SHUB]			= "shub",
-	[SMCA_SATA]			= "sata",
-	[SMCA_USB]			= "usb",
-	[SMCA_USR_DP]			= "usr_dp",
-	[SMCA_USR_CP]			= "usr_cp",
-	[SMCA_GMI_PCS]			= "gmi_pcs",
-	[SMCA_XGMI_PHY]			= "xgmi_phy",
-	[SMCA_WAFL_PHY]			= "wafl_phy",
-	[SMCA_GMI_PHY]			= "gmi_phy",
+	[SMCA_UMC]			= { "umc",		"Unified Memory Controller" },
+	[SMCA_UMC_V2]			= { "umc_v2",		"Unified Memory Controller v2" },
+	[SMCA_PB]			= { "param_block",	"Parameter Block" },
+	[SMCA_PSP ... SMCA_PSP_V2]	= { "psp",		"Platform Security Processor" },
+	[SMCA_SMU ... SMCA_SMU_V2]	= { "smu",		"System Management Unit" },
+	[SMCA_MP5]			= { "mp5",		"Microprocessor 5 Unit" },
+	[SMCA_MPDMA]			= { "mpdma",		"MPDMA Unit" },
+	[SMCA_NBIO]			= { "nbio",		"Northbridge IO Unit" },
+	[SMCA_PCIE ... SMCA_PCIE_V2]	= { "pcie",		"PCI Express Unit" },
+	[SMCA_XGMI_PCS]			= { "xgmi_pcs",		"Ext Global Memory Interconnect PCS Unit" },
+	[SMCA_NBIF]			= { "nbif",		"NBIF Unit" },
+	[SMCA_SHUB]			= { "shub",		"System Hub Unit" },
+	[SMCA_SATA]			= { "sata",		"SATA Unit" },
+	[SMCA_USB]			= { "usb",		"USB Unit" },
+	[SMCA_GMI_PCS]			= { "gmi_pcs",		"Global Memory Interconnect PCS Unit" },
+	[SMCA_XGMI_PHY]			= { "xgmi_phy",		"Ext Global Memory Interconnect PHY Unit" },
+	[SMCA_WAFL_PHY]			= { "wafl_phy",		"WAFL PHY Unit" },
+	[SMCA_GMI_PHY]			= { "gmi_phy",		"Global Memory Interconnect PHY Unit" },
 };
 
 static const char *smca_get_name(enum smca_bank_types t)
 {
 	if (t >= N_SMCA_BANK_TYPES)
 		return NULL;
 
-	return smca_names[t];
+	return smca_names[t].name;
 }
 
+const char *smca_get_long_name(enum smca_bank_types t)
+{
+	if (t >= N_SMCA_BANK_TYPES)
+		return NULL;
+
+	return smca_names[t].long_name;
+}
+EXPORT_SYMBOL_GPL(smca_get_long_name);
+
 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank)
 {
 	struct smca_bank *b;
@@ -167,7 +178,6 @@ static const struct smca_hwid smca_hwid_mcatypes[] = {
 	{ SMCA_CS,	 HWID_MCATYPE(0x2E, 0x0)	},
 	{ SMCA_PIE,	 HWID_MCATYPE(0x2E, 0x1)	},
 	{ SMCA_CS_V2,	 HWID_MCATYPE(0x2E, 0x2)	},
-	{ SMCA_MA_LLC,	 HWID_MCATYPE(0x2E, 0x4)	},
 
 	/* Unified Memory Controller MCA type */
 	{ SMCA_UMC,	 HWID_MCATYPE(0x96, 0x0)	},
@@ -202,8 +212,6 @@ static const struct smca_hwid smca_hwid_mcatypes[] = {
 	{ SMCA_SHUB,	 HWID_MCATYPE(0x80, 0x0)	},
 	{ SMCA_SATA,	 HWID_MCATYPE(0xA8, 0x0)	},
 	{ SMCA_USB,	 HWID_MCATYPE(0xAA, 0x0)	},
-	{ SMCA_USR_DP,	 HWID_MCATYPE(0x170, 0x0)	},
-	{ SMCA_USR_CP,	 HWID_MCATYPE(0x180, 0x0)	},
 	{ SMCA_GMI_PCS,  HWID_MCATYPE(0x241, 0x0)	},
 	{ SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0)	},
 	{ SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0)	},
@@ -707,13 +715,11 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
 
 bool amd_mce_is_memory_error(struct mce *m)
 {
-	enum smca_bank_types bank_type;
 	/* ErrCodeExt[20:16] */
 	u8 xec = (m->status >> 16) & 0x1f;
 
-	bank_type = smca_get_bank_type(m->extcpu, m->bank);
 	if (mce_flags.smca)
-		return (bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2) && xec == 0x0;
+		return smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC && xec == 0x0;
 
 	return m->bank == 4 && xec == 0x8;
 }
@@ -1043,7 +1049,7 @@ static const char *get_name(unsigned int cpu, unsigned int bank, struct threshol
 	if (bank_type >= N_SMCA_BANK_TYPES)
 		return NULL;
 
-	if (b && (bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2)) {
+	if (b && bank_type == SMCA_UMC) {
 		if (b->block < ARRAY_SIZE(smca_umc_block_names))
 			return smca_umc_block_names[b->block];
 		return NULL;