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dceraolodceraolo
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drm/xe/pxp: Add VCS inline termination support
The key termination is done with a specific submission to the VCS engine. This flow will be triggered in response to a termination interrupt, whose handling is coming in a follow-up patch in the series. v2: clean up defines and command emission code. (John) Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250129174140.948829-4-daniele.ceraolospurio@intel.com
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+156
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7 files changed

+156
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‎drivers/gpu/drm/xe/instructions/xe_instr_defs.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#define XE_INSTR_CMD_TYPE GENMASK(31, 29)
1717
#define XE_INSTR_MI REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x0)
1818
#define XE_INSTR_GSC REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x2)
19+
#define XE_INSTR_VIDEOPIPE REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x3)
1920
#define XE_INSTR_GFXPIPE REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x3)
2021
#define XE_INSTR_GFX_STATE REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x4)
2122

‎drivers/gpu/drm/xe/instructions/xe_mfx_commands.h‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2024 Intel Corporation
4+
*/
5+
6+
#ifndef _XE_MFX_COMMANDS_H_
7+
#define _XE_MFX_COMMANDS_H_
8+
9+
#include "instructions/xe_instr_defs.h"
10+
11+
#define MFX_CMD_SUBTYPE REG_GENMASK(28, 27) /* A.K.A cmd pipe */
12+
#define MFX_CMD_OPCODE REG_GENMASK(26, 24)
13+
#define MFX_CMD_SUB_OPCODE REG_GENMASK(23, 16)
14+
#define MFX_FLAGS_AND_LEN REG_GENMASK(15, 0)
15+
16+
#define XE_MFX_INSTR(subtype, op, sub_op) \
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(XE_INSTR_VIDEOPIPE | \
18+
REG_FIELD_PREP(MFX_CMD_SUBTYPE, subtype) | \
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REG_FIELD_PREP(MFX_CMD_OPCODE, op) | \
20+
REG_FIELD_PREP(MFX_CMD_SUB_OPCODE, sub_op))
21+
22+
#define MFX_WAIT XE_MFX_INSTR(1, 0, 0)
23+
#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG REG_BIT(9)
24+
#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG REG_BIT(8)
25+
26+
#define CRYPTO_KEY_EXCHANGE XE_MFX_INSTR(2, 6, 9)
27+
28+
#endif

‎drivers/gpu/drm/xe/instructions/xe_mi_commands.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,7 @@
4848
#define MI_LRI_LEN(x) (((x) & 0xff) + 1)
4949

5050
#define MI_FLUSH_DW __MI_INSTR(0x26)
51+
#define MI_FLUSH_DW_PROTECTED_MEM_EN REG_BIT(22)
5152
#define MI_FLUSH_DW_STORE_INDEX REG_BIT(21)
5253
#define MI_INVALIDATE_TLB REG_BIT(18)
5354
#define MI_FLUSH_DW_CCS REG_BIT(16)
@@ -66,4 +67,8 @@
6667

6768
#define MI_BATCH_BUFFER_START __MI_INSTR(0x31)
6869

70+
#define MI_SET_APPID __MI_INSTR(0x0e)
71+
#define MI_SET_APPID_SESSION_ID_MASK REG_GENMASK(6, 0)
72+
#define MI_SET_APPID_SESSION_ID(x) REG_FIELD_PREP(MI_SET_APPID_SESSION_ID_MASK, x)
73+
6974
#endif

‎drivers/gpu/drm/xe/xe_lrc.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,8 @@ struct xe_lrc_snapshot {
3939
u32 ctx_job_timestamp;
4040
};
4141

42-
#define LRC_PPHWSP_SCRATCH_ADDR (0x34 * 4)
42+
#define LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR (0x34 * 4)
43+
#define LRC_PPHWSP_PXP_INVAL_SCRATCH_ADDR (0x40 * 4)
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4445
struct xe_lrc *xe_lrc_create(struct xe_hw_engine *hwe, struct xe_vm *vm,
4546
u32 ring_size, u16 msix_vec);

‎drivers/gpu/drm/xe/xe_pxp_submit.c‎

Lines changed: 114 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,15 +5,21 @@
55

66
#include "xe_pxp_submit.h"
77

8+
#include <linux/delay.h>
89
#include <uapi/drm/xe_drm.h>
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1011
#include "xe_device_types.h"
12+
#include "xe_bb.h"
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#include "xe_bo.h"
1214
#include "xe_exec_queue.h"
1315
#include "xe_gsc_submit.h"
1416
#include "xe_gt.h"
17+
#include "xe_lrc.h"
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#include "xe_pxp_types.h"
19+
#include "xe_sched_job.h"
1620
#include "xe_vm.h"
21+
#include "instructions/xe_mfx_commands.h"
22+
#include "instructions/xe_mi_commands.h"
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/*
1925
* The VCS is used for kernel-owned GGTT submissions to issue key termination.
@@ -197,3 +203,111 @@ void xe_pxp_destroy_execution_resources(struct xe_pxp *pxp)
197203
destroy_gsc_client_resources(&pxp->gsc_res);
198204
destroy_vcs_execution_resources(pxp);
199205
}
206+
207+
#define emit_cmd(xe_, map_, offset_, val_) \
208+
xe_map_wr(xe_, map_, (offset_) * sizeof(u32), u32, val_)
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/* stall until prior PXP and MFX/HCP/HUC objects are completed */
211+
#define MFX_WAIT_PXP (MFX_WAIT | \
212+
MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | \
213+
MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG)
214+
static u32 pxp_emit_wait(struct xe_device *xe, struct iosys_map *batch, u32 offset)
215+
{
216+
/* wait for cmds to go through */
217+
emit_cmd(xe, batch, offset++, MFX_WAIT_PXP);
218+
emit_cmd(xe, batch, offset++, 0);
219+
220+
return offset;
221+
}
222+
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static u32 pxp_emit_session_selection(struct xe_device *xe, struct iosys_map *batch,
224+
u32 offset, u32 idx)
225+
{
226+
offset = pxp_emit_wait(xe, batch, offset);
227+
228+
/* pxp off */
229+
emit_cmd(xe, batch, offset++, MI_FLUSH_DW | MI_FLUSH_IMM_DW);
230+
emit_cmd(xe, batch, offset++, 0);
231+
emit_cmd(xe, batch, offset++, 0);
232+
emit_cmd(xe, batch, offset++, 0);
233+
234+
/* select session */
235+
emit_cmd(xe, batch, offset++, MI_SET_APPID | MI_SET_APPID_SESSION_ID(idx));
236+
emit_cmd(xe, batch, offset++, 0);
237+
238+
offset = pxp_emit_wait(xe, batch, offset);
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/* pxp on */
241+
emit_cmd(xe, batch, offset++, MI_FLUSH_DW |
242+
MI_FLUSH_DW_PROTECTED_MEM_EN |
243+
MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX |
244+
MI_FLUSH_IMM_DW);
245+
emit_cmd(xe, batch, offset++, LRC_PPHWSP_PXP_INVAL_SCRATCH_ADDR |
246+
MI_FLUSH_DW_USE_GTT);
247+
emit_cmd(xe, batch, offset++, 0);
248+
emit_cmd(xe, batch, offset++, 0);
249+
250+
offset = pxp_emit_wait(xe, batch, offset);
251+
252+
return offset;
253+
}
254+
255+
static u32 pxp_emit_inline_termination(struct xe_device *xe,
256+
struct iosys_map *batch, u32 offset)
257+
{
258+
/* session inline termination */
259+
emit_cmd(xe, batch, offset++, CRYPTO_KEY_EXCHANGE);
260+
emit_cmd(xe, batch, offset++, 0);
261+
262+
return offset;
263+
}
264+
265+
static u32 pxp_emit_session_termination(struct xe_device *xe, struct iosys_map *batch,
266+
u32 offset, u32 idx)
267+
{
268+
offset = pxp_emit_session_selection(xe, batch, offset, idx);
269+
offset = pxp_emit_inline_termination(xe, batch, offset);
270+
271+
return offset;
272+
}
273+
274+
/**
275+
* xe_pxp_submit_session_termination - submits a PXP inline termination
276+
* @pxp: the xe_pxp structure
277+
* @id: the session to terminate
278+
*
279+
* Emit an inline termination via the VCS engine to terminate a session.
280+
*
281+
* Returns 0 if the submission is successful, an errno value otherwise.
282+
*/
283+
int xe_pxp_submit_session_termination(struct xe_pxp *pxp, u32 id)
284+
{
285+
struct xe_sched_job *job;
286+
struct dma_fence *fence;
287+
long timeout;
288+
u32 offset = 0;
289+
u64 addr = xe_bo_ggtt_addr(pxp->vcs_exec.bo);
290+
291+
offset = pxp_emit_session_termination(pxp->xe, &pxp->vcs_exec.bo->vmap, offset, id);
292+
offset = pxp_emit_wait(pxp->xe, &pxp->vcs_exec.bo->vmap, offset);
293+
emit_cmd(pxp->xe, &pxp->vcs_exec.bo->vmap, offset, MI_BATCH_BUFFER_END);
294+
295+
job = xe_sched_job_create(pxp->vcs_exec.q, &addr);
296+
if (IS_ERR(job))
297+
return PTR_ERR(job);
298+
299+
xe_sched_job_arm(job);
300+
fence = dma_fence_get(&job->drm.s_fence->finished);
301+
xe_sched_job_push(job);
302+
303+
timeout = dma_fence_wait_timeout(fence, false, HZ);
304+
305+
dma_fence_put(fence);
306+
307+
if (!timeout)
308+
return -ETIMEDOUT;
309+
else if (timeout < 0)
310+
return timeout;
311+
312+
return 0;
313+
}

‎drivers/gpu/drm/xe/xe_pxp_submit.h‎

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Original file line numberDiff line numberDiff line change
@@ -6,9 +6,13 @@
66
#ifndef __XE_PXP_SUBMIT_H__
77
#define __XE_PXP_SUBMIT_H__
88

9+
#include <linux/types.h>
10+
911
struct xe_pxp;
1012

1113
int xe_pxp_allocate_execution_resources(struct xe_pxp *pxp);
1214
void xe_pxp_destroy_execution_resources(struct xe_pxp *pxp);
1315

16+
int xe_pxp_submit_session_termination(struct xe_pxp *pxp, u32 id);
17+
1418
#endif /* __XE_PXP_SUBMIT_H__ */

‎drivers/gpu/drm/xe/xe_ring_ops.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@ static int emit_flush_invalidate(u32 flag, u32 *dw, int i)
118118
dw[i++] |= MI_INVALIDATE_TLB | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW |
119119
MI_FLUSH_DW_STORE_INDEX;
120120

121-
dw[i++] = LRC_PPHWSP_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
121+
dw[i++] = LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
122122
dw[i++] = 0;
123123
dw[i++] = ~0U;
124124

@@ -156,7 +156,7 @@ static int emit_pipe_invalidate(u32 mask_flags, bool invalidate_tlb, u32 *dw,
156156

157157
flags &= ~mask_flags;
158158

159-
return emit_pipe_control(dw, i, 0, flags, LRC_PPHWSP_SCRATCH_ADDR, 0);
159+
return emit_pipe_control(dw, i, 0, flags, LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR, 0);
160160
}
161161

162162
static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,

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