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Ciprian Marian CosteaShawn Guo
Ciprian Marian Costea
authored and
Shawn Guo
committed
arm64: dts: s32g: Add S32G2/S32G3 uSDHC pinmux
Adding 100mhz & 200mhz pinmux support for uSDHC helps to enable higher speed modes for SD (SDR50, DDR50, SDR104) and eMMC (such as HS200, HS400/HS400ES). Signed-off-by: Radu Pirea <radu-nicolae.pirea@nxp.com> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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lines changed

5 files changed

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‎arch/arm64/boot/dts/freescale/s32g2.dtsi‎

Lines changed: 153 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -162,6 +162,159 @@
162162
slew-rate = <166>;
163163
};
164164
};
165+
166+
pinctrl_usdhc0: usdhc0grp-pins {
167+
usdhc0-grp0 {
168+
pinmux = <0x2e1>,
169+
<0x381>;
170+
output-enable;
171+
bias-pull-down;
172+
slew-rate = <150>;
173+
};
174+
175+
usdhc0-grp1 {
176+
pinmux = <0x2f1>,
177+
<0x301>,
178+
<0x311>,
179+
<0x321>,
180+
<0x331>,
181+
<0x341>,
182+
<0x351>,
183+
<0x361>,
184+
<0x371>;
185+
output-enable;
186+
input-enable;
187+
bias-pull-up;
188+
slew-rate = <150>;
189+
};
190+
191+
usdhc0-grp2 {
192+
pinmux = <0x391>;
193+
output-enable;
194+
slew-rate = <150>;
195+
};
196+
197+
usdhc0-grp3 {
198+
pinmux = <0x3a0>;
199+
input-enable;
200+
slew-rate = <150>;
201+
};
202+
203+
usdhc0-grp4 {
204+
pinmux = <0x2032>,
205+
<0x2042>,
206+
<0x2052>,
207+
<0x2062>,
208+
<0x2072>,
209+
<0x2082>,
210+
<0x2092>,
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<0x20a2>,
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<0x20b2>,
213+
<0x20c2>;
214+
};
215+
};
216+
217+
pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins {
218+
usdhc0-100mhz-grp0 {
219+
pinmux = <0x2e1>,
220+
<0x381>;
221+
output-enable;
222+
bias-pull-down;
223+
slew-rate = <150>;
224+
};
225+
226+
usdhc0-100mhz-grp1 {
227+
pinmux = <0x2f1>,
228+
<0x301>,
229+
<0x311>,
230+
<0x321>,
231+
<0x331>,
232+
<0x341>,
233+
<0x351>,
234+
<0x361>,
235+
<0x371>;
236+
output-enable;
237+
input-enable;
238+
bias-pull-up;
239+
slew-rate = <150>;
240+
};
241+
242+
usdhc0-100mhz-grp2 {
243+
pinmux = <0x391>;
244+
output-enable;
245+
slew-rate = <150>;
246+
};
247+
248+
usdhc0-100mhz-grp3 {
249+
pinmux = <0x3a0>;
250+
input-enable;
251+
slew-rate = <150>;
252+
};
253+
254+
usdhc0-100mhz-grp4 {
255+
pinmux = <0x2032>,
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<0x2042>,
257+
<0x2052>,
258+
<0x2062>,
259+
<0x2072>,
260+
<0x2082>,
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<0x2092>,
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<0x20a2>,
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<0x20b2>,
264+
<0x20c2>;
265+
};
266+
};
267+
268+
pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins {
269+
usdhc0-200mhz-grp0 {
270+
pinmux = <0x2e1>,
271+
<0x381>;
272+
output-enable;
273+
bias-pull-down;
274+
slew-rate = <208>;
275+
};
276+
277+
usdhc0-200mhz-grp1 {
278+
pinmux = <0x2f1>,
279+
<0x301>,
280+
<0x311>,
281+
<0x321>,
282+
<0x331>,
283+
<0x341>,
284+
<0x351>,
285+
<0x361>,
286+
<0x371>;
287+
output-enable;
288+
input-enable;
289+
bias-pull-up;
290+
slew-rate = <208>;
291+
};
292+
293+
usdhc0-200mhz-grp2 {
294+
pinmux = <0x391>;
295+
output-enable;
296+
slew-rate = <208>;
297+
};
298+
299+
usdhc0-200mhz-grp3 {
300+
pinmux = <0x3a0>;
301+
input-enable;
302+
slew-rate = <208>;
303+
};
304+
305+
usdhc0-200mhz-grp4 {
306+
pinmux = <0x2032>,
307+
<0x2042>,
308+
<0x2052>,
309+
<0x2062>,
310+
<0x2072>,
311+
<0x2082>,
312+
<0x2092>,
313+
<0x20a2>,
314+
<0x20b2>,
315+
<0x20c2>;
316+
};
317+
};
165318
};
166319

167320
uart0: serial@401c8000 {

‎arch/arm64/boot/dts/freescale/s32g274a-evb.dts‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,10 @@
3434
};
3535

3636
&usdhc0 {
37+
pinctrl-names = "default", "state_100mhz", "state_200mhz";
38+
pinctrl-0 = <&pinctrl_usdhc0>;
39+
pinctrl-1 = <&pinctrl_usdhc0_100mhz>;
40+
pinctrl-2 = <&pinctrl_usdhc0_200mhz>;
3741
disable-wp;
3842
status = "okay";
3943
};

‎arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,10 @@
4040
};
4141

4242
&usdhc0 {
43+
pinctrl-names = "default", "state_100mhz", "state_200mhz";
44+
pinctrl-0 = <&pinctrl_usdhc0>;
45+
pinctrl-1 = <&pinctrl_usdhc0_100mhz>;
46+
pinctrl-2 = <&pinctrl_usdhc0_200mhz>;
4347
disable-wp;
4448
status = "okay";
4549
};

‎arch/arm64/boot/dts/freescale/s32g3.dtsi‎

Lines changed: 153 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -219,6 +219,159 @@
219219
slew-rate = <166>;
220220
};
221221
};
222+
223+
pinctrl_usdhc0: usdhc0grp-pins {
224+
usdhc0-grp0 {
225+
pinmux = <0x2e1>,
226+
<0x381>;
227+
output-enable;
228+
bias-pull-down;
229+
slew-rate = <150>;
230+
};
231+
232+
usdhc0-grp1 {
233+
pinmux = <0x2f1>,
234+
<0x301>,
235+
<0x311>,
236+
<0x321>,
237+
<0x331>,
238+
<0x341>,
239+
<0x351>,
240+
<0x361>,
241+
<0x371>;
242+
output-enable;
243+
input-enable;
244+
bias-pull-up;
245+
slew-rate = <150>;
246+
};
247+
248+
usdhc0-grp2 {
249+
pinmux = <0x391>;
250+
output-enable;
251+
slew-rate = <150>;
252+
};
253+
254+
usdhc0-grp3 {
255+
pinmux = <0x3a0>;
256+
input-enable;
257+
slew-rate = <150>;
258+
};
259+
260+
usdhc0-grp4 {
261+
pinmux = <0x2032>,
262+
<0x2042>,
263+
<0x2052>,
264+
<0x2062>,
265+
<0x2072>,
266+
<0x2082>,
267+
<0x2092>,
268+
<0x20a2>,
269+
<0x20b2>,
270+
<0x20c2>;
271+
};
272+
};
273+
274+
pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins {
275+
usdhc0-100mhz-grp0 {
276+
pinmux = <0x2e1>,
277+
<0x381>;
278+
output-enable;
279+
bias-pull-down;
280+
slew-rate = <150>;
281+
};
282+
283+
usdhc0-100mhz-grp1 {
284+
pinmux = <0x2f1>,
285+
<0x301>,
286+
<0x311>,
287+
<0x321>,
288+
<0x331>,
289+
<0x341>,
290+
<0x351>,
291+
<0x361>,
292+
<0x371>;
293+
output-enable;
294+
input-enable;
295+
bias-pull-up;
296+
slew-rate = <150>;
297+
};
298+
299+
usdhc0-100mhz-grp2 {
300+
pinmux = <0x391>;
301+
output-enable;
302+
slew-rate = <150>;
303+
};
304+
305+
usdhc0-100mhz-grp3 {
306+
pinmux = <0x3a0>;
307+
input-enable;
308+
slew-rate = <150>;
309+
};
310+
311+
usdhc0-100mhz-grp4 {
312+
pinmux = <0x2032>,
313+
<0x2042>,
314+
<0x2052>,
315+
<0x2062>,
316+
<0x2072>,
317+
<0x2082>,
318+
<0x2092>,
319+
<0x20a2>,
320+
<0x20b2>,
321+
<0x20c2>;
322+
};
323+
};
324+
325+
pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins {
326+
usdhc0-200mhz-grp0 {
327+
pinmux = <0x2e1>,
328+
<0x381>;
329+
output-enable;
330+
bias-pull-down;
331+
slew-rate = <208>;
332+
};
333+
334+
usdhc0-200mhz-grp1 {
335+
pinmux = <0x2f1>,
336+
<0x301>,
337+
<0x311>,
338+
<0x321>,
339+
<0x331>,
340+
<0x341>,
341+
<0x351>,
342+
<0x361>,
343+
<0x371>;
344+
output-enable;
345+
input-enable;
346+
bias-pull-up;
347+
slew-rate = <208>;
348+
};
349+
350+
usdhc0-200mhz-grp2 {
351+
pinmux = <0x391>;
352+
output-enable;
353+
slew-rate = <208>;
354+
};
355+
356+
usdhc0-200mhz-grp3 {
357+
pinmux = <0x3a0>;
358+
input-enable;
359+
slew-rate = <208>;
360+
};
361+
362+
usdhc0-200mhz-grp4 {
363+
pinmux = <0x2032>,
364+
<0x2042>,
365+
<0x2052>,
366+
<0x2062>,
367+
<0x2072>,
368+
<0x2082>,
369+
<0x2092>,
370+
<0x20a2>,
371+
<0x20b2>,
372+
<0x20c2>;
373+
};
374+
};
222375
};
223376

224377
uart0: serial@401c8000 {

‎arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,10 @@
4040
};
4141

4242
&usdhc0 {
43+
pinctrl-names = "default", "state_100mhz", "state_200mhz";
44+
pinctrl-0 = <&pinctrl_usdhc0>;
45+
pinctrl-1 = <&pinctrl_usdhc0_100mhz>;
46+
pinctrl-2 = <&pinctrl_usdhc0_200mhz>;
4347
bus-width = <8>;
4448
disable-wp;
4549
status = "okay";

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