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drm/i915/display: convert intel_fifo_underrun.[ch] to struct intel_display
Going forward, struct intel_display is the main display device data pointer. Convert as much as possible of intel_fifo_underrun.[ch] to struct intel_display. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/682e667013e1726a6f2f78484b7e9618cee3b639.1739378096.git.jani.nikula@intel.com
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-67
lines changed

6 files changed

+67
-67
lines changed

‎drivers/gpu/drm/i915/display/intel_crtc.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -328,7 +328,7 @@ int intel_crtc_init(struct intel_display *display, enum pipe pipe)
328328
}
329329
crtc->plane_ids_mask |= BIT(primary->id);
330330

331-
intel_init_fifo_underrun_reporting(dev_priv, crtc, false);
331+
intel_init_fifo_underrun_reporting(display, crtc, false);
332332

333333
for_each_sprite(display, pipe, sprite) {
334334
struct intel_plane *plane;

‎drivers/gpu/drm/i915/display/intel_display.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7953,8 +7953,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
79537953
}
79547954

79557955
/* Underruns don't always raise interrupts, so check manually */
7956-
intel_check_cpu_fifo_underruns(dev_priv);
7957-
intel_check_pch_fifo_underruns(dev_priv);
7956+
intel_check_cpu_fifo_underruns(display);
7957+
intel_check_pch_fifo_underruns(display);
79587958

79597959
if (state->modeset)
79607960
intel_verify_planes(state);

‎drivers/gpu/drm/i915/display/intel_display_irq.c‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -562,7 +562,7 @@ void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
562562
i9xx_pipe_crc_irq_handler(dev_priv, pipe);
563563

564564
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
565-
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
565+
intel_cpu_fifo_underrun_irq_handler(display, pipe);
566566
}
567567

568568
if (blc_event || (iir & I915_ASLE_INTERRUPT))
@@ -587,7 +587,7 @@ void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
587587
i9xx_pipe_crc_irq_handler(dev_priv, pipe);
588588

589589
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
590-
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
590+
intel_cpu_fifo_underrun_irq_handler(display, pipe);
591591
}
592592

593593
if (blc_event || (iir & I915_ASLE_INTERRUPT))
@@ -614,7 +614,7 @@ void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
614614
i9xx_pipe_crc_irq_handler(dev_priv, pipe);
615615

616616
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
617-
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
617+
intel_cpu_fifo_underrun_irq_handler(display, pipe);
618618
}
619619

620620
if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
@@ -666,10 +666,10 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
666666
"PCH transcoder CRC error interrupt\n");
667667

668668
if (pch_iir & SDE_TRANSA_FIFO_UNDER)
669-
intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
669+
intel_pch_fifo_underrun_irq_handler(display, PIPE_A);
670670

671671
if (pch_iir & SDE_TRANSB_FIFO_UNDER)
672-
intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
672+
intel_pch_fifo_underrun_irq_handler(display, PIPE_B);
673673
}
674674

675675
static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
@@ -683,7 +683,7 @@ static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
683683

684684
for_each_pipe(dev_priv, pipe) {
685685
if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
686-
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
686+
intel_cpu_fifo_underrun_irq_handler(display, pipe);
687687

688688
if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
689689
if (IS_IVYBRIDGE(dev_priv))
@@ -707,7 +707,7 @@ static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
707707

708708
for_each_pipe(dev_priv, pipe)
709709
if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
710-
intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
710+
intel_pch_fifo_underrun_irq_handler(display, pipe);
711711

712712
intel_de_write(display, SERR_INT, serr_int);
713713
}
@@ -776,7 +776,7 @@ void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir)
776776
flip_done_handler(dev_priv, pipe);
777777

778778
if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
779-
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
779+
intel_cpu_fifo_underrun_irq_handler(display, pipe);
780780

781781
if (de_iir & DE_PIPE_CRC_DONE(pipe))
782782
i9xx_pipe_crc_irq_handler(dev_priv, pipe);
@@ -1228,7 +1228,7 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
12281228
hsw_pipe_crc_irq_handler(dev_priv, pipe);
12291229

12301230
if (iir & GEN8_PIPE_FIFO_UNDERRUN)
1231-
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1231+
intel_cpu_fifo_underrun_irq_handler(display, pipe);
12321232

12331233
fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
12341234
if (fault_errors)

‎drivers/gpu/drm/i915/display/intel_fifo_underrun.c‎

Lines changed: 47 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ static bool ivb_can_enable_err_int(struct intel_display *display)
6363

6464
lockdep_assert_held(&dev_priv->irq_lock);
6565

66-
for_each_pipe(dev_priv, pipe) {
66+
for_each_pipe(display, pipe) {
6767
crtc = intel_crtc_for_pipe(display, pipe);
6868

6969
if (crtc->cpu_fifo_underrun_disabled)
@@ -81,7 +81,7 @@ static bool cpt_can_enable_serr_int(struct intel_display *display)
8181

8282
lockdep_assert_held(&dev_priv->irq_lock);
8383

84-
for_each_pipe(dev_priv, pipe) {
84+
for_each_pipe(display, pipe) {
8585
crtc = intel_crtc_for_pipe(display, pipe);
8686

8787
if (crtc->pch_fifo_underrun_disabled)
@@ -95,40 +95,40 @@ static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
9595
{
9696
struct intel_display *display = to_intel_display(crtc);
9797
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
98-
i915_reg_t reg = PIPESTAT(dev_priv, crtc->pipe);
98+
i915_reg_t reg = PIPESTAT(display, crtc->pipe);
9999
u32 enable_mask;
100100

101101
lockdep_assert_held(&dev_priv->irq_lock);
102102

103-
if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
103+
if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
104104
return;
105105

106106
enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);
107-
intel_de_write(dev_priv, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
108-
intel_de_posting_read(dev_priv, reg);
107+
intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
108+
intel_de_posting_read(display, reg);
109109

110110
trace_intel_cpu_fifo_underrun(display, crtc->pipe);
111-
drm_err(&dev_priv->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));
111+
drm_err(display->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));
112112
}
113113

114114
static void i9xx_set_fifo_underrun_reporting(struct intel_display *display,
115115
enum pipe pipe,
116116
bool enable, bool old)
117117
{
118118
struct drm_i915_private *dev_priv = to_i915(display->drm);
119-
i915_reg_t reg = PIPESTAT(dev_priv, pipe);
119+
i915_reg_t reg = PIPESTAT(display, pipe);
120120

121121
lockdep_assert_held(&dev_priv->irq_lock);
122122

123123
if (enable) {
124124
u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
125125

126-
intel_de_write(dev_priv, reg,
126+
intel_de_write(display, reg,
127127
enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
128-
intel_de_posting_read(dev_priv, reg);
128+
intel_de_posting_read(display, reg);
129129
} else {
130-
if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS)
131-
drm_err(&dev_priv->drm, "pipe %c underrun\n",
130+
if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS)
131+
drm_err(display->drm, "pipe %c underrun\n",
132132
pipe_name(pipe));
133133
}
134134
}
@@ -151,18 +151,18 @@ static void ivb_check_fifo_underruns(struct intel_crtc *crtc)
151151
struct intel_display *display = to_intel_display(crtc);
152152
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
153153
enum pipe pipe = crtc->pipe;
154-
u32 err_int = intel_de_read(dev_priv, GEN7_ERR_INT);
154+
u32 err_int = intel_de_read(display, GEN7_ERR_INT);
155155

156156
lockdep_assert_held(&dev_priv->irq_lock);
157157

158158
if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)
159159
return;
160160

161-
intel_de_write(dev_priv, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
162-
intel_de_posting_read(dev_priv, GEN7_ERR_INT);
161+
intel_de_write(display, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
162+
intel_de_posting_read(display, GEN7_ERR_INT);
163163

164164
trace_intel_cpu_fifo_underrun(display, pipe);
165-
drm_err(&dev_priv->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));
165+
drm_err(display->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));
166166
}
167167

168168
static void ivb_set_fifo_underrun_reporting(struct intel_display *display,
@@ -171,7 +171,7 @@ static void ivb_set_fifo_underrun_reporting(struct intel_display *display,
171171
{
172172
struct drm_i915_private *dev_priv = to_i915(display->drm);
173173
if (enable) {
174-
intel_de_write(dev_priv, GEN7_ERR_INT,
174+
intel_de_write(display, GEN7_ERR_INT,
175175
ERR_INT_FIFO_UNDERRUN(pipe));
176176

177177
if (!ivb_can_enable_err_int(display))
@@ -182,8 +182,8 @@ static void ivb_set_fifo_underrun_reporting(struct intel_display *display,
182182
ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
183183

184184
if (old &&
185-
intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
186-
drm_err(&dev_priv->drm,
185+
intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
186+
drm_err(display->drm,
187187
"uncleared fifo underrun on pipe %c\n",
188188
pipe_name(pipe));
189189
}
@@ -220,19 +220,19 @@ static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc)
220220
struct intel_display *display = to_intel_display(crtc);
221221
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
222222
enum pipe pch_transcoder = crtc->pipe;
223-
u32 serr_int = intel_de_read(dev_priv, SERR_INT);
223+
u32 serr_int = intel_de_read(display, SERR_INT);
224224

225225
lockdep_assert_held(&dev_priv->irq_lock);
226226

227227
if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0)
228228
return;
229229

230-
intel_de_write(dev_priv, SERR_INT,
230+
intel_de_write(display, SERR_INT,
231231
SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
232-
intel_de_posting_read(dev_priv, SERR_INT);
232+
intel_de_posting_read(display, SERR_INT);
233233

234234
trace_intel_pch_fifo_underrun(display, pch_transcoder);
235-
drm_err(&dev_priv->drm, "pch fifo underrun on pch transcoder %c\n",
235+
drm_err(display->drm, "pch fifo underrun on pch transcoder %c\n",
236236
pipe_name(pch_transcoder));
237237
}
238238

@@ -243,7 +243,7 @@ static void cpt_set_fifo_underrun_reporting(struct intel_display *display,
243243
struct drm_i915_private *dev_priv = to_i915(display->drm);
244244

245245
if (enable) {
246-
intel_de_write(dev_priv, SERR_INT,
246+
intel_de_write(display, SERR_INT,
247247
SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
248248

249249
if (!cpt_can_enable_serr_int(display))
@@ -253,9 +253,9 @@ static void cpt_set_fifo_underrun_reporting(struct intel_display *display,
253253
} else {
254254
ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
255255

256-
if (old && intel_de_read(dev_priv, SERR_INT) &
256+
if (old && intel_de_read(display, SERR_INT) &
257257
SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
258-
drm_err(&dev_priv->drm,
258+
drm_err(display->drm,
259259
"uncleared pch fifo underrun on pch transcoder %c\n",
260260
pipe_name(pch_transcoder));
261261
}
@@ -368,81 +368,79 @@ bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,
368368

369369
/**
370370
* intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
371-
* @dev_priv: i915 device instance
371+
* @display: display device instance
372372
* @pipe: (CPU) pipe to set state for
373373
*
374374
* This handles a CPU fifo underrun interrupt, generating an underrun warning
375375
* into dmesg if underrun reporting is enabled and then disables the underrun
376376
* interrupt to avoid an irq storm.
377377
*/
378-
void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
378+
void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,
379379
enum pipe pipe)
380380
{
381-
struct intel_display *display = &dev_priv->display;
382381
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
383382

384383
/* We may be called too early in init, thanks BIOS! */
385384
if (crtc == NULL)
386385
return;
387386

388387
/* GMCH can't disable fifo underruns, filter them. */
389-
if (HAS_GMCH(dev_priv) &&
388+
if (HAS_GMCH(display) &&
390389
crtc->cpu_fifo_underrun_disabled)
391390
return;
392391

393392
if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) {
394393
trace_intel_cpu_fifo_underrun(display, pipe);
395394

396-
drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
395+
drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
397396
}
398397

399-
intel_fbc_handle_fifo_underrun_irq(&dev_priv->display);
398+
intel_fbc_handle_fifo_underrun_irq(display);
400399
}
401400

402401
/**
403402
* intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt
404-
* @dev_priv: i915 device instance
403+
* @display: display device instance
405404
* @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
406405
*
407406
* This handles a PCH fifo underrun interrupt, generating an underrun warning
408407
* into dmesg if underrun reporting is enabled and then disables the underrun
409408
* interrupt to avoid an irq storm.
410409
*/
411-
void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
410+
void intel_pch_fifo_underrun_irq_handler(struct intel_display *display,
412411
enum pipe pch_transcoder)
413412
{
414-
struct intel_display *display = &dev_priv->display;
415-
416413
if (intel_set_pch_fifo_underrun_reporting(display, pch_transcoder,
417414
false)) {
418415
trace_intel_pch_fifo_underrun(display, pch_transcoder);
419-
drm_err(&dev_priv->drm, "PCH transcoder %c FIFO underrun\n",
416+
drm_err(display->drm, "PCH transcoder %c FIFO underrun\n",
420417
pipe_name(pch_transcoder));
421418
}
422419
}
423420

424421
/**
425422
* intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately
426-
* @dev_priv: i915 device instance
423+
* @display: display device instance
427424
*
428425
* Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared
429426
* error interrupt may have been disabled, and so CPU fifo underruns won't
430427
* necessarily raise an interrupt, and on GMCH platforms where underruns never
431428
* raise an interrupt.
432429
*/
433-
void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
430+
void intel_check_cpu_fifo_underruns(struct intel_display *display)
434431
{
432+
struct drm_i915_private *dev_priv = to_i915(display->drm);
435433
struct intel_crtc *crtc;
436434

437435
spin_lock_irq(&dev_priv->irq_lock);
438436

439-
for_each_intel_crtc(&dev_priv->drm, crtc) {
437+
for_each_intel_crtc(display->drm, crtc) {
440438
if (crtc->cpu_fifo_underrun_disabled)
441439
continue;
442440

443-
if (HAS_GMCH(dev_priv))
441+
if (HAS_GMCH(display))
444442
i9xx_check_fifo_underruns(crtc);
445-
else if (DISPLAY_VER(dev_priv) == 7)
443+
else if (DISPLAY_VER(display) == 7)
446444
ivb_check_fifo_underruns(crtc);
447445
}
448446

@@ -451,19 +449,20 @@ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
451449

452450
/**
453451
* intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately
454-
* @dev_priv: i915 device instance
452+
* @display: display device instance
455453
*
456454
* Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared
457455
* error interrupt may have been disabled, and so PCH fifo underruns won't
458456
* necessarily raise an interrupt.
459457
*/
460-
void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
458+
void intel_check_pch_fifo_underruns(struct intel_display *display)
461459
{
460+
struct drm_i915_private *dev_priv = to_i915(display->drm);
462461
struct intel_crtc *crtc;
463462

464463
spin_lock_irq(&dev_priv->irq_lock);
465464

466-
for_each_intel_crtc(&dev_priv->drm, crtc) {
465+
for_each_intel_crtc(display->drm, crtc) {
467466
if (crtc->pch_fifo_underrun_disabled)
468467
continue;
469468

@@ -474,10 +473,12 @@ void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
474473
spin_unlock_irq(&dev_priv->irq_lock);
475474
}
476475

477-
void intel_init_fifo_underrun_reporting(struct drm_i915_private *i915,
476+
void intel_init_fifo_underrun_reporting(struct intel_display *display,
478477
struct intel_crtc *crtc,
479478
bool enable)
480479
{
480+
struct drm_i915_private *i915 = to_i915(display->drm);
481+
481482
crtc->cpu_fifo_underrun_disabled = !enable;
482483

483484
/*

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