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Sumit Guptathierryreding
Sumit Gupta
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thierryreding
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soc/tegra: cbb: Add support for CBB fabrics in Tegra264
Add support for CBB 2.0 based fabrics in Tegra264 SoC using DT. Fabrics reporting errors are: SYSTEM, TOP0, UPHY0 and VISION. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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‎drivers/soc/tegra/cbb/tegra234-cbb.c‎

Lines changed: 279 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,34 @@ enum tegra234_cbb_fabric_ids {
8989
T234_MAX_FABRIC_ID,
9090
};
9191

92+
enum tegra264_cbb_fabric_ids {
93+
T264_SYSTEM_CBB_FABRIC_ID,
94+
T264_TOP_0_CBB_FABRIC_ID,
95+
T264_VISION_CBB_FABRIC_ID,
96+
T264_DISP_USB_CBB_FABRIC_ID,
97+
T264_UPHY0_CBB_FABRIC_ID,
98+
T264_RSVD0_FABRIC_ID,
99+
T264_RSVD1_FABRIC_ID,
100+
T264_RSVD2_FABRIC_ID,
101+
T264_RSVD3_FABRIC_ID,
102+
T264_RSVD4_FABRIC_ID,
103+
T264_RSVD5_FABRIC_ID,
104+
T264_AON_FABRIC_ID,
105+
T264_PSC_FABRIC_ID,
106+
T264_OESP_FABRIC_ID,
107+
T264_APE_FABRIC_ID,
108+
T264_BPMP_FABRIC_ID,
109+
T264_RCE_0_FABRIC_ID,
110+
T264_RCE_1_FABRIC_ID,
111+
T264_RSVD6_FABRIC_ID,
112+
T264_DCE_FABRIC_ID,
113+
T264_FSI_FABRIC_ID,
114+
T264_ISC_FABRIC_ID,
115+
T264_SB_FABRIC_ID,
116+
T264_ISC_CPU_FABRIC_ID,
117+
T264_RSVD7_FABRIC_ID,
118+
};
119+
92120
struct tegra234_target_lookup {
93121
const char *name;
94122
unsigned int offset;
@@ -455,6 +483,17 @@ static void print_errlog_err(struct seq_file *file, struct tegra234_cbb *cbb)
455483
tegra_cbb_print_err(file, "\t Fabric\t\t: %s (id:%#x)\n",
456484
cbb->fabric->fab_list[fab_id].name, fab_id);
457485

486+
if (of_machine_is_compatible("nvidia,tegra264") && fab_id == T264_UPHY0_CBB_FABRIC_ID) {
487+
/*
488+
* In T264, AON Fabric ID value is incorrectly same as UPHY0 fabric ID.
489+
* For 'ID = 0x4', we must check for the address which caused the error
490+
* to find the correct fabric which returned error.
491+
*/
492+
tegra_cbb_print_err(file, "\t or Fabric\t\t: %s\n",
493+
cbb->fabric->fab_list[T264_AON_FABRIC_ID].name);
494+
tegra_cbb_print_err(file, "\t Please use Address to determine correct fabric.\n");
495+
}
496+
458497
tegra_cbb_print_err(file, "\t Target_Id\t\t: %#x\n", target_id);
459498
tegra_cbb_print_err(file, "\t Burst_length\t\t: %#x\n", burst_length);
460499
tegra_cbb_print_err(file, "\t Burst_type\t\t: %#x\n", burst_type);
@@ -1143,13 +1182,253 @@ static const struct tegra234_cbb_fabric tegra241_bpmp_fabric = {
11431182
.firewall_wr_ctl = 0x8e8,
11441183
};
11451184

1185+
static const char * const tegra264_initiator_id[] = {
1186+
[0x0] = "TZ",
1187+
[0x1] = "CCPLEX",
1188+
[0x2] = "ISC",
1189+
[0x3] = "BPMP_FW",
1190+
[0x4] = "AON",
1191+
[0x5] = "MSS_SEQ",
1192+
[0x6] = "GPCDMA_P",
1193+
[0x7] = "TSECA_NONSECURE",
1194+
[0x8] = "TSECA_LIGHTSECURE",
1195+
[0x9] = "TSECA_HEAVYSECURE",
1196+
[0xa] = "CORESIGHT",
1197+
[0xb] = "APE_0",
1198+
[0xc] = "APE_1",
1199+
[0xd] = "PEATRANS",
1200+
[0xe] = "JTAGM_DFT",
1201+
[0xf] = "RCE",
1202+
[0x10] = "DCE",
1203+
[0x11] = "PSC_FW_USER",
1204+
[0x12] = "PSC_FW_SUPERVISOR",
1205+
[0x13] = "PSC_FW_MACHINE",
1206+
[0x14] = "PSC_BOOT",
1207+
[0x15] = "BPMP_BOOT",
1208+
[0x16] = "GPU_0",
1209+
[0x17] = "GPU_1",
1210+
[0x18] = "GPU_2",
1211+
[0x19] = "GPU_3",
1212+
[0x1a] = "GPU_4",
1213+
[0x1b] = "PSC_EXT_BOOT",
1214+
[0x1c] = "PSC_EXT_RUNTIME",
1215+
[0x1d] = "OESP_EXT",
1216+
[0x1e] = "SB_EXT",
1217+
[0x1f] = "FSI_SAFETY_0",
1218+
[0x20] = "FSI_SAFETY_1",
1219+
[0x21] = "FSI_SAFETY_2",
1220+
[0x22] = "FSI_SAFETY_3",
1221+
[0x23] = "FSI_CHSM",
1222+
[0x24] = "RCE_1",
1223+
[0x25] = "BPMP_OEM_FW",
1224+
[0x26 ... 0x3d] = "RSVD",
1225+
[0x3e] = "CBB_SMN",
1226+
[0x3f] = "CBB_RSVD"
1227+
};
1228+
1229+
static const struct tegra234_target_lookup tegra264_top0_cbb_target_map[] = {
1230+
{ "RSVD", 0x000000 },
1231+
{ "CBB_CENTRAL", 0xC020000 },
1232+
{ "AXI2APB_1", 0x80000 },
1233+
{ "AXI2APB_10", 0x81000 },
1234+
{ "AXI2APB_11", 0x82000 },
1235+
{ "RSVD", 0x00000 },
1236+
{ "RSVD", 0x00000 },
1237+
{ "AXI2APB_14", 0x83000 },
1238+
{ "AXI2APB_15", 0x84000 },
1239+
{ "AXI2APB_16", 0x85000 },
1240+
{ "AXI2APB_17", 0x86000 },
1241+
{ "AXI2APB_2", 0x87000 },
1242+
{ "AXI2APB_3", 0x88000 },
1243+
{ "RSVD", 0x00000 },
1244+
{ "AXI2APB_5", 0x8A000 },
1245+
{ "AXI2APB_6", 0x8B000 },
1246+
{ "AXI2APB_7", 0x8C000 },
1247+
{ "AXI2APB_8", 0x8D000 },
1248+
{ "AXI2APB_9", 0x8E000 },
1249+
{ "FSI_SLAVE", 0x64000 },
1250+
{ "DISP_USB_CBB_T", 0x65000 },
1251+
{ "SYSTEM_CBB_T", 0x66000 },
1252+
{ "UPHY0_CBB_T", 0x67000 },
1253+
{ "VISION_CBB_T", 0x68000 },
1254+
{ "CCPLEX_SLAVE", 0x69000 },
1255+
{ "PCIE_C0", 0x6A000 },
1256+
{ "SMN_UCF_RX_0", 0x6B000 },
1257+
{ "SMN_UCF_RX_1", 0x6C000 },
1258+
{ "AXI2APB_4", 0x89000 },
1259+
};
1260+
1261+
static const struct tegra234_target_lookup tegra264_sys_cbb_target_map[] = {
1262+
{ "RSVD", 0x00000 },
1263+
{ "AXI2APB_1", 0xE1000 },
1264+
{ "RSVD", 0x00000 },
1265+
{ "AON_SLAVE", 0x79000 },
1266+
{ "APE_SLAVE", 0x73000 },
1267+
{ "BPMP_SLAVE", 0x74000 },
1268+
{ "OESP_SLAVE", 0x75000 },
1269+
{ "PSC_SLAVE", 0x76000 },
1270+
{ "SB_SLAVE", 0x7A000 },
1271+
{ "SMN_SYSTEM_RX", 0x7B000 },
1272+
{ "STM", 0x77000 },
1273+
{ "RSVD", 0x00000 },
1274+
{ "AXI2APB_3", 0xE3000 },
1275+
{ "TOP_CBB_T", 0x7C000 },
1276+
{ "AXI2APB_2", 0xE4000 },
1277+
{ "AXI2APB_4", 0xE5000 },
1278+
{ "AXI2APB_5", 0xE6000 },
1279+
};
1280+
1281+
static const struct tegra234_target_lookup tegra264_uphy0_cbb_target_map[] = {
1282+
[0 ... 20] = { "RSVD", 0x00000 },
1283+
{ "AXI2APB_1", 0x71000 },
1284+
{ "RSVD", 0x00000 },
1285+
{ "AXI2APB_3", 0x75000 },
1286+
{ "SMN_UPHY0_RX", 0x53000 },
1287+
{ "RSVD", 0x00000 },
1288+
{ "RSVD", 0x00000 },
1289+
{ "RSVD", 0x00000 },
1290+
{ "RSVD", 0x00000 },
1291+
{ "PCIE_C4", 0x4B000 },
1292+
{ "AXI2APB_2", 0x74000 },
1293+
{ "AXI2APB_4", 0x76000 },
1294+
{ "AXI2APB_5", 0x77000 },
1295+
{ "RSVD", 0x00000 },
1296+
{ "AXI2APB_7", 0x79000 },
1297+
{ "PCIE_C2", 0x56000 },
1298+
{ "RSVD", 0x00000 },
1299+
{ "RSVD", 0x00000 },
1300+
{ "PCIE_C1", 0x55000 },
1301+
{ "RSVD", 0x00000 },
1302+
{ "AXI2APB_10", 0x72000 },
1303+
{ "AXI2APB_11", 0x7C000 },
1304+
{ "AXI2APB_8", 0x7A000 },
1305+
{ "AXI2APB_9", 0x7B000 },
1306+
{ "RSVD", 0x00000 },
1307+
{ "RSVD", 0x00000 },
1308+
{ "PCIE_C5", 0x4E000 },
1309+
{ "PCIE_C3", 0x58000 },
1310+
{ "RSVD", 0x00000 },
1311+
{ "ISC_SLAVE", 0x54000 },
1312+
{ "TOP_CBB_T", 0x57000 },
1313+
{ "AXI2APB_12", 0x7D000 },
1314+
{ "AXI2APB_13", 0x70000 },
1315+
{ "AXI2APB_6", 0x7E000 },
1316+
};
1317+
1318+
static const struct tegra234_target_lookup tegra264_vision_cbb_target_map[] = {
1319+
[0 ... 5] = { "RSVD", 0x0 },
1320+
{ "HOST1X", 0x45000 },
1321+
{ "RSVD", 0x00000 },
1322+
{ "RSVD", 0x00000 },
1323+
{ "AXI2APB_2", 0x71000 },
1324+
{ "RSVD", 0x00000 },
1325+
{ "RSVD", 0x00000 },
1326+
{ "SMN_VISION_RX", 0x47000 },
1327+
[13 ... 19] = { "RSVD", 0x0 },
1328+
{ "RCE_0_SLAVE", 0x4B000 },
1329+
{ "RCE_1_SLAVE", 0x4C000 },
1330+
{ "AXI2APB_1", 0x72000 },
1331+
{ "AXI2APB_3", 0x73000 },
1332+
{ "TOP_CBB_T", 0x4D000 },
1333+
1334+
};
1335+
1336+
static const struct tegra234_fabric_lookup tegra264_cbb_fab_list[] = {
1337+
[T264_SYSTEM_CBB_FABRIC_ID] = { "system-cbb-fabric", true,
1338+
tegra264_sys_cbb_target_map,
1339+
ARRAY_SIZE(tegra264_sys_cbb_target_map) },
1340+
[T264_TOP_0_CBB_FABRIC_ID] = { "top0-cbb-fabric", true,
1341+
tegra264_top0_cbb_target_map,
1342+
ARRAY_SIZE(tegra264_top0_cbb_target_map) },
1343+
[T264_VISION_CBB_FABRIC_ID] = { "vision-cbb-fabric", true,
1344+
tegra264_vision_cbb_target_map,
1345+
ARRAY_SIZE(tegra264_vision_cbb_target_map) },
1346+
[T264_DISP_USB_CBB_FABRIC_ID] = { "disp-usb-cbb-fabric" },
1347+
[T264_UPHY0_CBB_FABRIC_ID] = { "uphy0-cbb-fabric", true,
1348+
tegra264_uphy0_cbb_target_map,
1349+
ARRAY_SIZE(tegra264_uphy0_cbb_target_map) },
1350+
[T264_AON_FABRIC_ID] = { "aon-fabric" },
1351+
[T264_PSC_FABRIC_ID] = { "psc-fabric" },
1352+
[T264_OESP_FABRIC_ID] = { "oesp-fabric" },
1353+
[T264_APE_FABRIC_ID] = { "ape-fabirc" },
1354+
[T264_BPMP_FABRIC_ID] = { "bpmp-fabric" },
1355+
[T264_RCE_0_FABRIC_ID] = { "rce0-fabric" },
1356+
[T264_RCE_1_FABRIC_ID] = { "rce1-fabric" },
1357+
[T264_DCE_FABRIC_ID] = { "dce-fabric" },
1358+
[T264_FSI_FABRIC_ID] = { "fsi-fabric" },
1359+
[T264_ISC_FABRIC_ID] = { "isc-fabric" },
1360+
[T264_SB_FABRIC_ID] = { "sb-fabric" },
1361+
[T264_ISC_CPU_FABRIC_ID] = { "isc-cpu-fabric" },
1362+
};
1363+
1364+
static const struct tegra234_cbb_fabric tegra264_top0_cbb_fabric = {
1365+
.fab_id = T264_TOP_0_CBB_FABRIC_ID,
1366+
.fab_list = tegra264_cbb_fab_list,
1367+
.initiator_id = tegra264_initiator_id,
1368+
.errors = tegra241_cbb_errors,
1369+
.max_errors = ARRAY_SIZE(tegra241_cbb_errors),
1370+
.err_intr_enbl = 0x7,
1371+
.err_status_clr = 0x1ff007f,
1372+
.notifier_offset = 0x90000,
1373+
.off_mask_erd = 0x4a004,
1374+
.firewall_base = 0x3c0000,
1375+
.firewall_ctl = 0x5b0,
1376+
.firewall_wr_ctl = 0x5a8,
1377+
};
1378+
1379+
static const struct tegra234_cbb_fabric tegra264_sys_cbb_fabric = {
1380+
.fab_id = T264_SYSTEM_CBB_FABRIC_ID,
1381+
.fab_list = tegra264_cbb_fab_list,
1382+
.initiator_id = tegra264_initiator_id,
1383+
.errors = tegra241_cbb_errors,
1384+
.max_errors = ARRAY_SIZE(tegra241_cbb_errors),
1385+
.err_intr_enbl = 0xf,
1386+
.err_status_clr = 0x1ff007f,
1387+
.notifier_offset = 0x40000,
1388+
.firewall_base = 0x29c000,
1389+
.firewall_ctl = 0x170,
1390+
.firewall_wr_ctl = 0x168,
1391+
};
1392+
1393+
static const struct tegra234_cbb_fabric tegra264_uphy0_cbb_fabric = {
1394+
.fab_id = T264_UPHY0_CBB_FABRIC_ID,
1395+
.fab_list = tegra264_cbb_fab_list,
1396+
.initiator_id = tegra264_initiator_id,
1397+
.errors = tegra241_cbb_errors,
1398+
.max_errors = ARRAY_SIZE(tegra241_cbb_errors),
1399+
.err_intr_enbl = 0x1,
1400+
.err_status_clr = 0x1ff007f,
1401+
.notifier_offset = 0x80000,
1402+
.firewall_base = 0x360000,
1403+
.firewall_ctl = 0x590,
1404+
.firewall_wr_ctl = 0x588,
1405+
};
1406+
1407+
static const struct tegra234_cbb_fabric tegra264_vision_cbb_fabric = {
1408+
.fab_id = T264_VISION_CBB_FABRIC_ID,
1409+
.fab_list = tegra264_cbb_fab_list,
1410+
.initiator_id = tegra264_initiator_id,
1411+
.errors = tegra241_cbb_errors,
1412+
.max_errors = ARRAY_SIZE(tegra241_cbb_errors),
1413+
.err_intr_enbl = 0x1,
1414+
.err_status_clr = 0x1ff007f,
1415+
.notifier_offset = 0x80000,
1416+
.firewall_base = 0x290000,
1417+
.firewall_ctl = 0x5d0,
1418+
.firewall_wr_ctl = 0x5c8,
1419+
};
1420+
11461421
static const struct of_device_id tegra234_cbb_dt_ids[] = {
11471422
{ .compatible = "nvidia,tegra234-cbb-fabric", .data = &tegra234_cbb_fabric },
11481423
{ .compatible = "nvidia,tegra234-aon-fabric", .data = &tegra234_aon_fabric },
11491424
{ .compatible = "nvidia,tegra234-bpmp-fabric", .data = &tegra234_bpmp_fabric },
11501425
{ .compatible = "nvidia,tegra234-dce-fabric", .data = &tegra234_dce_fabric },
11511426
{ .compatible = "nvidia,tegra234-rce-fabric", .data = &tegra234_rce_fabric },
11521427
{ .compatible = "nvidia,tegra234-sce-fabric", .data = &tegra234_sce_fabric },
1428+
{ .compatible = "nvidia,tegra264-sys-cbb-fabric", .data = &tegra264_sys_cbb_fabric },
1429+
{ .compatible = "nvidia,tegra264-top0-cbb-fabric", .data = &tegra264_top0_cbb_fabric },
1430+
{ .compatible = "nvidia,tegra264-uphy0-cbb-fabric", .data = &tegra264_uphy0_cbb_fabric },
1431+
{ .compatible = "nvidia,tegra264-vision-cbb-fabric", .data = &tegra264_vision_cbb_fabric },
11531432
{ /* sentinel */ },
11541433
};
11551434
MODULE_DEVICE_TABLE(of, tegra234_cbb_dt_ids);

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