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johnharr-inteljohnharr-intel
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drm/xe/guc: Cache DSS info when creating capture register list
Calculating the DSS id (index of a steered register) currently requires reading state from the hwconfig table and that currently requires dynamically allocating memory. The GuC based register capture (for dev core dumps) includes this index as part of the register name in the dump. However, it was calculating said index at the time of the dump for every dump. That is wasteful. It also breaks anyone trying to do the dump at a time when memory allocations are not allowed. So rather than calculating on every print, just calculate at start of day when creating the register list in the first place. Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://lore.kernel.org/r/20250417213303.3021243-1-John.C.Harrison@Intel.com
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‎drivers/gpu/drm/xe/xe_guc_capture.c‎

Lines changed: 46 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -105,49 +105,49 @@ struct __guc_capture_parsed_output {
105105
* 3. Incorrect order will trigger XE_WARN.
106106
*/
107107
#define COMMON_XELP_BASE_GLOBAL \
108-
{ FORCEWAKE_GT, REG_32BIT, 0, 0, "FORCEWAKE_GT"}
108+
{ FORCEWAKE_GT, REG_32BIT, 0, 0, 0, "FORCEWAKE_GT"}
109109

110110
#define COMMON_BASE_ENGINE_INSTANCE \
111-
{ RING_HWSTAM(0), REG_32BIT, 0, 0, "HWSTAM"}, \
112-
{ RING_HWS_PGA(0), REG_32BIT, 0, 0, "RING_HWS_PGA"}, \
113-
{ RING_HEAD(0), REG_32BIT, 0, 0, "RING_HEAD"}, \
114-
{ RING_TAIL(0), REG_32BIT, 0, 0, "RING_TAIL"}, \
115-
{ RING_CTL(0), REG_32BIT, 0, 0, "RING_CTL"}, \
116-
{ RING_MI_MODE(0), REG_32BIT, 0, 0, "RING_MI_MODE"}, \
117-
{ RING_MODE(0), REG_32BIT, 0, 0, "RING_MODE"}, \
118-
{ RING_ESR(0), REG_32BIT, 0, 0, "RING_ESR"}, \
119-
{ RING_EMR(0), REG_32BIT, 0, 0, "RING_EMR"}, \
120-
{ RING_EIR(0), REG_32BIT, 0, 0, "RING_EIR"}, \
121-
{ RING_IMR(0), REG_32BIT, 0, 0, "RING_IMR"}, \
122-
{ RING_IPEHR(0), REG_32BIT, 0, 0, "IPEHR"}, \
123-
{ RING_INSTDONE(0), REG_32BIT, 0, 0, "RING_INSTDONE"}, \
124-
{ INDIRECT_RING_STATE(0), REG_32BIT, 0, 0, "INDIRECT_RING_STATE"}, \
125-
{ RING_ACTHD(0), REG_64BIT_LOW_DW, 0, 0, NULL}, \
126-
{ RING_ACTHD_UDW(0), REG_64BIT_HI_DW, 0, 0, "ACTHD"}, \
127-
{ RING_BBADDR(0), REG_64BIT_LOW_DW, 0, 0, NULL}, \
128-
{ RING_BBADDR_UDW(0), REG_64BIT_HI_DW, 0, 0, "RING_BBADDR"}, \
129-
{ RING_START(0), REG_64BIT_LOW_DW, 0, 0, NULL}, \
130-
{ RING_START_UDW(0), REG_64BIT_HI_DW, 0, 0, "RING_START"}, \
131-
{ RING_DMA_FADD(0), REG_64BIT_LOW_DW, 0, 0, NULL}, \
132-
{ RING_DMA_FADD_UDW(0), REG_64BIT_HI_DW, 0, 0, "RING_DMA_FADD"}, \
133-
{ RING_EXECLIST_STATUS_LO(0), REG_64BIT_LOW_DW, 0, 0, NULL}, \
134-
{ RING_EXECLIST_STATUS_HI(0), REG_64BIT_HI_DW, 0, 0, "RING_EXECLIST_STATUS"}, \
135-
{ RING_EXECLIST_SQ_CONTENTS_LO(0), REG_64BIT_LOW_DW, 0, 0, NULL}, \
136-
{ RING_EXECLIST_SQ_CONTENTS_HI(0), REG_64BIT_HI_DW, 0, 0, "RING_EXECLIST_SQ_CONTENTS"}
111+
{ RING_HWSTAM(0), REG_32BIT, 0, 0, 0, "HWSTAM"}, \
112+
{ RING_HWS_PGA(0), REG_32BIT, 0, 0, 0, "RING_HWS_PGA"}, \
113+
{ RING_HEAD(0), REG_32BIT, 0, 0, 0, "RING_HEAD"}, \
114+
{ RING_TAIL(0), REG_32BIT, 0, 0, 0, "RING_TAIL"}, \
115+
{ RING_CTL(0), REG_32BIT, 0, 0, 0, "RING_CTL"}, \
116+
{ RING_MI_MODE(0), REG_32BIT, 0, 0, 0, "RING_MI_MODE"}, \
117+
{ RING_MODE(0), REG_32BIT, 0, 0, 0, "RING_MODE"}, \
118+
{ RING_ESR(0), REG_32BIT, 0, 0, 0, "RING_ESR"}, \
119+
{ RING_EMR(0), REG_32BIT, 0, 0, 0, "RING_EMR"}, \
120+
{ RING_EIR(0), REG_32BIT, 0, 0, 0, "RING_EIR"}, \
121+
{ RING_IMR(0), REG_32BIT, 0, 0, 0, "RING_IMR"}, \
122+
{ RING_IPEHR(0), REG_32BIT, 0, 0, 0, "IPEHR"}, \
123+
{ RING_INSTDONE(0), REG_32BIT, 0, 0, 0, "RING_INSTDONE"}, \
124+
{ INDIRECT_RING_STATE(0), REG_32BIT, 0, 0, 0, "INDIRECT_RING_STATE"}, \
125+
{ RING_ACTHD(0), REG_64BIT_LOW_DW, 0, 0, 0, NULL}, \
126+
{ RING_ACTHD_UDW(0), REG_64BIT_HI_DW, 0, 0, 0, "ACTHD"}, \
127+
{ RING_BBADDR(0), REG_64BIT_LOW_DW, 0, 0, 0, NULL}, \
128+
{ RING_BBADDR_UDW(0), REG_64BIT_HI_DW, 0, 0, 0, "RING_BBADDR"}, \
129+
{ RING_START(0), REG_64BIT_LOW_DW, 0, 0, 0, NULL}, \
130+
{ RING_START_UDW(0), REG_64BIT_HI_DW, 0, 0, 0, "RING_START"}, \
131+
{ RING_DMA_FADD(0), REG_64BIT_LOW_DW, 0, 0, 0, NULL}, \
132+
{ RING_DMA_FADD_UDW(0), REG_64BIT_HI_DW, 0, 0, 0, "RING_DMA_FADD"}, \
133+
{ RING_EXECLIST_STATUS_LO(0), REG_64BIT_LOW_DW, 0, 0, 0, NULL}, \
134+
{ RING_EXECLIST_STATUS_HI(0), REG_64BIT_HI_DW, 0, 0, 0, "RING_EXECLIST_STATUS"}, \
135+
{ RING_EXECLIST_SQ_CONTENTS_LO(0), REG_64BIT_LOW_DW, 0, 0, 0, NULL}, \
136+
{ RING_EXECLIST_SQ_CONTENTS_HI(0), REG_64BIT_HI_DW, 0, 0, 0, "RING_EXECLIST_SQ_CONTENTS"}
137137

138138
#define COMMON_XELP_RC_CLASS \
139-
{ RCU_MODE, REG_32BIT, 0, 0, "RCU_MODE"}
139+
{ RCU_MODE, REG_32BIT, 0, 0, 0, "RCU_MODE"}
140140

141141
#define COMMON_XELP_RC_CLASS_INSTDONE \
142-
{ SC_INSTDONE, REG_32BIT, 0, 0, "SC_INSTDONE"}, \
143-
{ SC_INSTDONE_EXTRA, REG_32BIT, 0, 0, "SC_INSTDONE_EXTRA"}, \
144-
{ SC_INSTDONE_EXTRA2, REG_32BIT, 0, 0, "SC_INSTDONE_EXTRA2"}
142+
{ SC_INSTDONE, REG_32BIT, 0, 0, 0, "SC_INSTDONE"}, \
143+
{ SC_INSTDONE_EXTRA, REG_32BIT, 0, 0, 0, "SC_INSTDONE_EXTRA"}, \
144+
{ SC_INSTDONE_EXTRA2, REG_32BIT, 0, 0, 0, "SC_INSTDONE_EXTRA2"}
145145

146146
#define XELP_VEC_CLASS_REGS \
147-
{ SFC_DONE(0), 0, 0, 0, "SFC_DONE[0]"}, \
148-
{ SFC_DONE(1), 0, 0, 0, "SFC_DONE[1]"}, \
149-
{ SFC_DONE(2), 0, 0, 0, "SFC_DONE[2]"}, \
150-
{ SFC_DONE(3), 0, 0, 0, "SFC_DONE[3]"}
147+
{ SFC_DONE(0), 0, 0, 0, 0, "SFC_DONE[0]"}, \
148+
{ SFC_DONE(1), 0, 0, 0, 0, "SFC_DONE[1]"}, \
149+
{ SFC_DONE(2), 0, 0, 0, 0, "SFC_DONE[2]"}, \
150+
{ SFC_DONE(3), 0, 0, 0, 0, "SFC_DONE[3]"}
151151

152152
/* XE_LP Global */
153153
static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = {
@@ -352,7 +352,7 @@ static const struct __ext_steer_reg xehpg_extregs[] = {
352352

353353
static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
354354
const struct __ext_steer_reg *extlist,
355-
int slice_id, int subslice_id)
355+
u32 dss_id, u16 slice_id, u16 subslice_id)
356356
{
357357
if (!ext || !extlist)
358358
return;
@@ -361,6 +361,7 @@ static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
361361
ext->flags = FIELD_PREP(GUC_REGSET_STEERING_NEEDED, 1);
362362
ext->flags |= FIELD_PREP(GUC_REGSET_STEERING_GROUP, slice_id);
363363
ext->flags |= FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, subslice_id);
364+
ext->dss_id = dss_id;
364365
ext->regname = extlist->name;
365366
}
366367

@@ -397,7 +398,7 @@ static void guc_capture_alloc_steered_lists(struct xe_guc *guc)
397398
{
398399
struct xe_gt *gt = guc_to_gt(guc);
399400
u16 slice, subslice;
400-
int iter, i, total = 0;
401+
int dss, i, total = 0;
401402
const struct __guc_mmio_reg_descr_group *lists = guc->capture->reglists;
402403
const struct __guc_mmio_reg_descr_group *list;
403404
struct __guc_mmio_reg_descr_group *extlists;
@@ -454,15 +455,15 @@ static void guc_capture_alloc_steered_lists(struct xe_guc *guc)
454455

455456
/* For steering registers, the list is generated at run-time */
456457
extarray = (struct __guc_mmio_reg_descr *)extlists[0].list;
457-
for_each_dss_steering(iter, gt, slice, subslice) {
458+
for_each_dss_steering(dss, gt, slice, subslice) {
458459
for (i = 0; i < ARRAY_SIZE(xe_extregs); ++i) {
459-
__fill_ext_reg(extarray, &xe_extregs[i], slice, subslice);
460+
__fill_ext_reg(extarray, &xe_extregs[i], dss, slice, subslice);
460461
++extarray;
461462
}
462463

463464
if (has_xehpg_extregs)
464465
for (i = 0; i < ARRAY_SIZE(xehpg_extregs); ++i) {
465-
__fill_ext_reg(extarray, &xehpg_extregs[i], slice, subslice);
466+
__fill_ext_reg(extarray, &xehpg_extregs[i], dss, slice, subslice);
466467
++extarray;
467468
}
468469
}
@@ -1747,17 +1748,12 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
17471748
*/
17481749
XE_WARN_ON(low32_ready);
17491750

1750-
if (FIELD_GET(GUC_REGSET_STEERING_NEEDED, reg_desc->flags)) {
1751-
int dss, group, instance;
1752-
1753-
group = FIELD_GET(GUC_REGSET_STEERING_GROUP, reg_desc->flags);
1754-
instance = FIELD_GET(GUC_REGSET_STEERING_INSTANCE, reg_desc->flags);
1755-
dss = xe_gt_mcr_steering_info_to_dss_id(gt, group, instance);
1756-
1757-
drm_printf(p, "\t%s[%u]: 0x%08x\n", reg_desc->regname, dss, value);
1758-
} else {
1751+
if (FIELD_GET(GUC_REGSET_STEERING_NEEDED, reg_desc->flags))
1752+
drm_printf(p, "\t%s[%u]: 0x%08x\n", reg_desc->regname,
1753+
reg_desc->dss_id, value);
1754+
else
17591755
drm_printf(p, "\t%s: 0x%08x\n", reg_desc->regname, value);
1760-
}
1756+
17611757
break;
17621758
}
17631759
}

‎drivers/gpu/drm/xe/xe_guc_capture_types.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,8 @@ struct __guc_mmio_reg_descr {
3939
u32 flags;
4040
/** @mask: The mask to apply */
4141
u32 mask;
42+
/** @dss_id: Cached index for steered registers */
43+
u32 dss_id;
4244
/** @regname: Name of the register */
4345
const char *regname;
4446
};

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