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Michael Chankuba-moo
Michael Chan
authored and
kuba-moo
committed
bnxt_en: Update firmware interface spec to 1.10.3.85
The major change is the new firmware command to flush the FW debug logs to the host backing store context memory buffers. Reviewed-by: Hongguang Gao <hongguang.gao@broadcom.com> Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com> Signed-off-by: Michael Chan <michael.chan@broadcom.com> Link: https://patch.msgid.link/20241115151438.550106-2-michael.chan@broadcom.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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‎drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h‎

Lines changed: 136 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,10 @@ struct hwrm_resp_hdr {
4242
#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL
4343
#define TLV_TYPE_QUERY_ROCE_CC_GEN2 0x6UL
4444
#define TLV_TYPE_MODIFY_ROCE_CC_GEN2 0x7UL
45+
#define TLV_TYPE_QUERY_ROCE_CC_GEN1_EXT 0x8UL
46+
#define TLV_TYPE_MODIFY_ROCE_CC_GEN1_EXT 0x9UL
47+
#define TLV_TYPE_QUERY_ROCE_CC_GEN2_EXT 0xaUL
48+
#define TLV_TYPE_MODIFY_ROCE_CC_GEN2_EXT 0xbUL
4549
#define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL
4650
#define TLV_TYPE_ENGINE_CKV_IV 0x8003UL
4751
#define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL
@@ -509,6 +513,7 @@ struct cmd_nums {
509513
#define HWRM_TFC_IF_TBL_GET 0x399UL
510514
#define HWRM_TFC_TBL_SCOPE_CONFIG_GET 0x39aUL
511515
#define HWRM_TFC_RESC_USAGE_QUERY 0x39bUL
516+
#define HWRM_TFC_GLOBAL_ID_FREE 0x39cUL
512517
#define HWRM_SV 0x400UL
513518
#define HWRM_DBG_SERDES_TEST 0xff0eUL
514519
#define HWRM_DBG_LOG_BUFFER_FLUSH 0xff0fUL
@@ -624,8 +629,8 @@ struct hwrm_err_output {
624629
#define HWRM_VERSION_MAJOR 1
625630
#define HWRM_VERSION_MINOR 10
626631
#define HWRM_VERSION_UPDATE 3
627-
#define HWRM_VERSION_RSVD 68
628-
#define HWRM_VERSION_STR "1.10.3.68"
632+
#define HWRM_VERSION_RSVD 85
633+
#define HWRM_VERSION_STR "1.10.3.85"
629634

630635
/* hwrm_ver_get_input (size:192b/24B) */
631636
struct hwrm_ver_get_input {
@@ -1302,6 +1307,43 @@ struct hwrm_async_event_cmpl_error_report {
13021307
#define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0
13031308
};
13041309

1310+
/* hwrm_async_event_cmpl_dbg_buf_producer (size:128b/16B) */
1311+
struct hwrm_async_event_cmpl_dbg_buf_producer {
1312+
__le16 type;
1313+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_MASK 0x3fUL
1314+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_SFT 0
1315+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1316+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT
1317+
__le16 event_id;
1318+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER 0x4cUL
1319+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER
1320+
__le32 event_data2;
1321+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURR_OFF_MASK 0xffffffffUL
1322+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURR_OFF_SFT 0
1323+
u8 opaque_v;
1324+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_V 0x1UL
1325+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_MASK 0xfeUL
1326+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_SFT 1
1327+
u8 timestamp_lo;
1328+
__le16 timestamp_hi;
1329+
__le32 event_data1;
1330+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MASK 0xffffUL
1331+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SFT 0
1332+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT_TRACE 0x0UL
1333+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT2_TRACE 0x1UL
1334+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT_TRACE 0x2UL
1335+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT2_TRACE 0x3UL
1336+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP0_TRACE 0x4UL
1337+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_L2_HWRM_TRACE 0x5UL
1338+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE 0x6UL
1339+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA0_TRACE 0x7UL
1340+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA1_TRACE 0x8UL
1341+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA2_TRACE 0x9UL
1342+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP1_TRACE 0xaUL
1343+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_AFM_KONG_HWRM_TRACE 0xbUL
1344+
#define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_AFM_KONG_HWRM_TRACE
1345+
};
1346+
13051347
/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
13061348
struct hwrm_async_event_cmpl_hwrm_error {
13071349
__le16 type;
@@ -1864,7 +1906,10 @@ struct hwrm_func_qcaps_output {
18641906
__le32 roce_vf_max_gid;
18651907
__le32 flags_ext3;
18661908
#define FUNC_QCAPS_RESP_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP 0x1UL
1867-
u8 unused_3[7];
1909+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_REQUIRE_L2_FILTER 0x2UL
1910+
#define FUNC_QCAPS_RESP_FLAGS_EXT3_MAX_ROCE_VFS_SUPPORTED 0x4UL
1911+
__le16 max_roce_vfs;
1912+
u8 unused_3[5];
18681913
u8 valid;
18691914
};
18701915

@@ -2253,17 +2298,18 @@ struct hwrm_func_cfg_input {
22532298
#define FUNC_CFG_REQ_FLAGS2_KTLS_KEY_CTX_ASSETS_TEST 0x1UL
22542299
#define FUNC_CFG_REQ_FLAGS2_QUIC_KEY_CTX_ASSETS_TEST 0x2UL
22552300
__le32 enables2;
2256-
#define FUNC_CFG_REQ_ENABLES2_KDNET 0x1UL
2257-
#define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE 0x2UL
2258-
#define FUNC_CFG_REQ_ENABLES2_QUIC_TX_KEY_CTXS 0x4UL
2259-
#define FUNC_CFG_REQ_ENABLES2_QUIC_RX_KEY_CTXS 0x8UL
2260-
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_AV_PER_VF 0x10UL
2261-
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_CQ_PER_VF 0x20UL
2262-
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_MRW_PER_VF 0x40UL
2263-
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_QP_PER_VF 0x80UL
2264-
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_SRQ_PER_VF 0x100UL
2265-
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_GID_PER_VF 0x200UL
2266-
#define FUNC_CFG_REQ_ENABLES2_XID_PARTITION_CFG 0x400UL
2301+
#define FUNC_CFG_REQ_ENABLES2_KDNET 0x1UL
2302+
#define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE 0x2UL
2303+
#define FUNC_CFG_REQ_ENABLES2_QUIC_TX_KEY_CTXS 0x4UL
2304+
#define FUNC_CFG_REQ_ENABLES2_QUIC_RX_KEY_CTXS 0x8UL
2305+
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_AV_PER_VF 0x10UL
2306+
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_CQ_PER_VF 0x20UL
2307+
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_MRW_PER_VF 0x40UL
2308+
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_QP_PER_VF 0x80UL
2309+
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_SRQ_PER_VF 0x100UL
2310+
#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_GID_PER_VF 0x200UL
2311+
#define FUNC_CFG_REQ_ENABLES2_XID_PARTITION_CFG 0x400UL
2312+
#define FUNC_CFG_REQ_ENABLES2_PHYSICAL_SLOT_NUMBER 0x800UL
22672313
u8 port_kdnet_mode;
22682314
#define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL
22692315
#define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 0x1UL
@@ -2281,7 +2327,7 @@ struct hwrm_func_cfg_input {
22812327
#define FUNC_CFG_REQ_DB_PAGE_SIZE_2MB 0x9UL
22822328
#define FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 0xaUL
22832329
#define FUNC_CFG_REQ_DB_PAGE_SIZE_LAST FUNC_CFG_REQ_DB_PAGE_SIZE_4MB
2284-
u8 unused_1[2];
2330+
__le16 physical_slot_number;
22852331
__le32 num_ktls_tx_key_ctxs;
22862332
__le32 num_ktls_rx_key_ctxs;
22872333
__le32 num_quic_tx_key_ctxs;
@@ -3683,7 +3729,7 @@ struct hwrm_func_ptp_ext_qcfg_output {
36833729
u8 valid;
36843730
};
36853731

3686-
/* hwrm_func_backing_store_cfg_v2_input (size:448b/56B) */
3732+
/* hwrm_func_backing_store_cfg_v2_input (size:512b/64B) */
36873733
struct hwrm_func_backing_store_cfg_v2_input {
36883734
__le16 req_type;
36893735
__le16 cmpl_ring;
@@ -3721,6 +3767,7 @@ struct hwrm_func_backing_store_cfg_v2_input {
37213767
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA1_TRACE 0x27UL
37223768
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA2_TRACE 0x28UL
37233769
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP1_TRACE 0x29UL
3770+
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL
37243771
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL
37253772
#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID
37263773
__le16 instance;
@@ -3752,6 +3799,9 @@ struct hwrm_func_backing_store_cfg_v2_input {
37523799
__le32 split_entry_1;
37533800
__le32 split_entry_2;
37543801
__le32 split_entry_3;
3802+
__le32 enables;
3803+
#define FUNC_BACKING_STORE_CFG_V2_REQ_ENABLES_NEXT_BS_OFFSET 0x1UL
3804+
__le32 next_bs_offset;
37553805
};
37563806

37573807
/* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */
@@ -3802,6 +3852,7 @@ struct hwrm_func_backing_store_qcfg_v2_input {
38023852
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA1_TRACE 0x27UL
38033853
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA2_TRACE 0x28UL
38043854
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP1_TRACE 0x29UL
3855+
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL
38053856
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL
38063857
#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID
38073858
__le16 instance;
@@ -3963,6 +4014,7 @@ struct hwrm_func_backing_store_qcaps_v2_input {
39634014
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA1_TRACE 0x27UL
39644015
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA2_TRACE 0x28UL
39654016
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP1_TRACE 0x29UL
4017+
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL
39664018
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL
39674019
#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID
39684020
u8 rsvd[6];
@@ -4005,6 +4057,7 @@ struct hwrm_func_backing_store_qcaps_v2_output {
40054057
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA1_TRACE 0x27UL
40064058
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA2_TRACE 0x28UL
40074059
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP1_TRACE 0x29UL
4060+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL
40084061
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL
40094062
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID
40104063
__le16 entry_size;
@@ -4014,6 +4067,8 @@ struct hwrm_func_backing_store_qcaps_v2_output {
40144067
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_DRIVER_MANAGED_MEMORY 0x4UL
40154068
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC 0x8UL
40164069
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_DBG_TRACE 0x10UL
4070+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_BIN_DBG_TRACE 0x20UL
4071+
#define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_NEXT_BS_OFFSET 0x40UL
40174072
__le32 instance_bit_map;
40184073
u8 ctx_init_value;
40194074
u8 ctx_init_offset;
@@ -4034,7 +4089,8 @@ struct hwrm_func_backing_store_qcaps_v2_output {
40344089
__le32 split_entry_1;
40354090
__le32 split_entry_2;
40364091
__le32 split_entry_3;
4037-
u8 rsvd3[3];
4092+
__le16 max_instance_count;
4093+
u8 rsvd3;
40384094
u8 valid;
40394095
};
40404096

@@ -4535,11 +4591,12 @@ struct hwrm_port_phy_qcfg_output {
45354591
#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8 0x3dUL
45364592
#define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8
45374593
u8 media_type;
4538-
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
4539-
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL
4540-
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL
4541-
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL
4542-
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE
4594+
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
4595+
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL
4596+
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL
4597+
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL
4598+
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_BACKPLANE 0x4UL
4599+
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_BACKPLANE
45434600
u8 xcvr_pkg_type;
45444601
#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL
45454602
#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL
@@ -4654,7 +4711,8 @@ struct hwrm_port_phy_qcfg_output {
46544711
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL
46554712
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL
46564713
u8 link_down_reason;
4657-
#define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL
4714+
#define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL
4715+
#define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_OTP_SPEED_VIOLATION 0x2UL
46584716
__le16 support_speeds2;
46594717
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB 0x1UL
46604718
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB 0x2UL
@@ -9241,20 +9299,22 @@ struct hwrm_fw_set_time_output {
92419299
/* hwrm_struct_hdr (size:128b/16B) */
92429300
struct hwrm_struct_hdr {
92439301
__le16 struct_id;
9244-
#define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL
9245-
#define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL
9246-
#define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL
9247-
#define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL
9248-
#define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
9249-
#define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL
9250-
#define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
9251-
#define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL
9252-
#define STRUCT_HDR_STRUCT_ID_PEER_MMAP 0x429UL
9253-
#define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL
9254-
#define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
9255-
#define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL
9256-
#define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL
9257-
#define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF
9302+
#define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL
9303+
#define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL
9304+
#define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL
9305+
#define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL
9306+
#define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
9307+
#define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL
9308+
#define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
9309+
#define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL
9310+
#define STRUCT_HDR_STRUCT_ID_PEER_MMAP 0x429UL
9311+
#define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL
9312+
#define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
9313+
#define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL
9314+
#define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL
9315+
#define STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_COUNT 0x12cUL
9316+
#define STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_BOUND 0x12dUL
9317+
#define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_BOUND
92589318
__le16 len;
92599319
u8 version;
92609320
u8 count;
@@ -9756,6 +9816,7 @@ struct hwrm_dbg_qcaps_output {
97569816
#define DBG_QCAPS_RESP_FLAGS_COREDUMP_HOST_DDR 0x10UL
97579817
#define DBG_QCAPS_RESP_FLAGS_COREDUMP_HOST_CAPTURE 0x20UL
97589818
#define DBG_QCAPS_RESP_FLAGS_PTRACE 0x40UL
9819+
#define DBG_QCAPS_RESP_FLAGS_REG_ACCESS_RESTRICTED 0x80UL
97599820
u8 unused_1[3];
97609821
u8 valid;
97619822
};
@@ -9996,6 +10057,43 @@ struct hwrm_dbg_ring_info_get_output {
999610057
u8 valid;
999710058
};
999810059

10060+
/* hwrm_dbg_log_buffer_flush_input (size:192b/24B) */
10061+
struct hwrm_dbg_log_buffer_flush_input {
10062+
__le16 req_type;
10063+
__le16 cmpl_ring;
10064+
__le16 seq_id;
10065+
__le16 target_id;
10066+
__le64 resp_addr;
10067+
__le16 type;
10068+
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_SRT_TRACE 0x0UL
10069+
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_SRT2_TRACE 0x1UL
10070+
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CRT_TRACE 0x2UL
10071+
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CRT2_TRACE 0x3UL
10072+
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_RIGP0_TRACE 0x4UL
10073+
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_L2_HWRM_TRACE 0x5UL
10074+
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_ROCE_HWRM_TRACE 0x6UL
10075+
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA0_TRACE 0x7UL
10076+
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA1_TRACE 0x8UL
10077+
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA2_TRACE 0x9UL
10078+
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_RIGP1_TRACE 0xaUL
10079+
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_AFM_KONG_HWRM_TRACE 0xbUL
10080+
#define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_LAST DBG_LOG_BUFFER_FLUSH_REQ_TYPE_AFM_KONG_HWRM_TRACE
10081+
u8 unused_1[2];
10082+
__le32 flags;
10083+
#define DBG_LOG_BUFFER_FLUSH_REQ_FLAGS_FLUSH_ALL_BUFFERS 0x1UL
10084+
};
10085+
10086+
/* hwrm_dbg_log_buffer_flush_output (size:128b/16B) */
10087+
struct hwrm_dbg_log_buffer_flush_output {
10088+
__le16 error_code;
10089+
__le16 req_type;
10090+
__le16 seq_id;
10091+
__le16 resp_len;
10092+
__le32 current_buffer_offset;
10093+
u8 unused_1[3];
10094+
u8 valid;
10095+
};
10096+
999910097
/* hwrm_nvm_read_input (size:320b/40B) */
1000010098
struct hwrm_nvm_read_input {
1000110099
__le16 req_type;
@@ -10080,6 +10178,7 @@ struct hwrm_nvm_write_input {
1008010178
#define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL
1008110179
#define NVM_WRITE_REQ_FLAGS_BATCH_MODE 0x2UL
1008210180
#define NVM_WRITE_REQ_FLAGS_BATCH_LAST 0x4UL
10181+
#define NVM_WRITE_REQ_FLAGS_SKIP_CRID_CHECK 0x8UL
1008310182
__le32 dir_item_length;
1008410183
__le32 offset;
1008510184
__le32 len;

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