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dadongshangu/README.md

Anurag's github stats

  • 📫 Reach me on mail: dadongshangu@outlook.com
  • 📫 Reach me on wechat: ddvalley
  • 🔭 I’m currently working on ASIC logic design. I am also interested in Perl/Python/UVM/Design flow/Design methodology;
  • 🌱 I’m currently learning UVM verification /Python /AI /Ethernet;
  • ⚡ Fun: I would like to take photos and essay writing. And I am one member of Toastmasters Club;
  • ⚡ Blog: https://dadongshangu.github.io/
  • ⚡ Wechat official account on essay: 大东山谷
  • ⚡ Wechat official account on ASIC design: 数字逻辑电路小站
  • ⚡ My photos: Michael's photos

Popular repositories Loading

  1. async_FIFO async_FIFO Public

    This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)

    SystemVerilog 54 15

  2. hw hw Public

    Forked from nvdla/hw

    RTL, Cmodel, and testbench for NVDLA

    Verilog 1

  3. synthesis_example synthesis_example Public

    This is one example of synthesis. And trying some options.

    Tcl 1

  4. CDN CDN Public

    my CDN pictures

  5. dadongshangu.github.io dadongshangu.github.io Public

    Github pages

    Stylus

  6. dadongshangu dadongshangu Public