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1. PicoRV32-SoC-Design PicoRV32-SoC-Design Public

   Design and implementation of a System-on-Chip (SoC) based on the PicoRV32 RISC-V CPU core. The SoC integrates various IPs, including memory, SPI memory interface, UART, and memory decoding logic. T…

   1

2. AXI4_Master-Slave_design AXI4_Master-Slave_design Public

   AXI4 Master-Slave bus design, capable of burst read/write operations. Ensured modularity for integration into SoC designs.

   SystemVerilog

3. L1-L2-Cache-Controller L1-L2-Cache-Controller Public

   Implementation of an L1 and L2 cache controller in Verilog. It is designed to be simulated using Icarus Verilog (iverilog) and GTKWave.

   Verilog

4. AXI4_uvmVerify AXI4_uvmVerify Public

   Verification of an AXI4-Lite interface using the Universal Verification Methodology (UVM).

   SystemVerilog

5. APB-Master-Slave-bus APB-Master-Slave-bus Public

   APB (Advanced Peripheral Bus) Master-Slave interface along with a testbench and RAM memory module. The design is structured to support asynchronous clocking between the Master and Slave components

   SystemVerilog

6. RISC-Processor RISC-Processor Public

   A Verilog RTL of 8-bit, pipeline based RISC processor

   Verilog 1