RISC-microprocessor

A Verilog RTL of RISC processor with data and branch hazard correction pipeline

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
Nexys3_master.ucf		Nexys3_master.ucf
README.md		README.md
VGA_driver.v		VGA_driver.v
accessory.v		accessory.v
alu.v		alu.v
clock_100to25.v		clock_100to25.v
color_converter.v		color_converter.v
datahazard.v		datahazard.v
datamemory.v		datamemory.v
image q3.pdf		image q3.pdf
input_output.v		input_output.v
instructiondecoder.v		instructiondecoder.v
mcu_io.v		mcu_io.v
microcontroller_main.v		microcontroller_main.v
programmemory.v		programmemory.v
registerfile.v		registerfile.v
vga_grid16.v		vga_grid16.v
vga_out.v		vga_out.v

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