Merge pull request #1333 from diffblue/error-unpacked-struct-assignment

Verilog: refuse assignments of other types to unpacked structs

Author: tautschnig

regression/verilog/structs/unpacked_struct2.desc

@@ -0,0 +1,7 @@
+CORE
+unpacked_struct2.sv
+
+^file .* line 9: failed to convert `signed \[31:0\]' to `struct'$
+^EXIT=2$
+^SIGNAL=0$
+--

regression/verilog/structs/unpacked_struct2.sv

@@ -0,0 +1,11 @@
+module main;
+
+  // an unpacked struct type
+  typedef struct {
+    bit field;
+  } s_type;
+
+  // bit-vectors cannot be assigned to unpacked structs
+  wire s_type w = 123;
+
+endmodule

src/verilog/verilog_typecheck_expr.cpp

@@ -223,6 +223,14 @@ void verilog_typecheck_exprt::assignment_conversion(
   if(lhs_type == rhs.type())
     return;
 
+  if(lhs_type.id() == ID_struct && !lhs_type.get_bool(ID_packed))
+  {
+    // assignment of a non-matching type to unpacked struct
+    throw errort().with_location(rhs.source_location())
+      << "failed to convert `" << to_string(original_rhs_type) << "' to `"
+      << to_string(lhs_type) << "'";
+  }
+
   // do enum, union and struct decay
   enum_decay(rhs);
   struct_decay(rhs);