Merge pull request #1451 from diffblue/time1

SystemVerilog: test for time data type

Author: tautschnig

regression/verilog/data-types/time1.desc

@@ -0,0 +1,7 @@
+CORE
+time1.sv
+--bound -
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring

regression/verilog/data-types/time1.sv

@@ -0,0 +1,12 @@
+module main;
+
+  initial begin : some_block
+    time some_time;
+    some_time = 1;
+    assert(some_time == 1);
+    some_time++;
+    assert(some_time == 2);
+    assert($bits(some_time) == 64);
+  end
+
+endmodule