Verilog: cleanout unused Boolean operators from type checker #1290
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
The Boolean ID_xor, ID_xnor, ID_nand, ID_nor are only ever generated as output by the Verilog type checker, and should never be inputs. This removes the case that handles them as inputs.
tautschnig
reviewed
Oct 2, 2025
Comment on lines
+3525
to
+3531
| else if( | ||
| expr.id() == ID_xor || expr.id() == ID_xnor || expr.id() == ID_nand || | ||
| expr.id() == ID_nor) | ||
| { | ||
| // should not occur -- only generated by the typechecker | ||
| PRECONDITION(false); | ||
| } |
There was a problem hiding this comment.
The n_input_gatetype in the parser has all these - should the parser be changed as well, or am I misreading this?
There was a problem hiding this comment.
This is just the gate type, and doesn't turn into an expression before synthesis.
tautschnig
approved these changes
Oct 2, 2025
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
The Boolean
ID_xor,ID_xnor,ID_nand,ID_norare only ever generated as output by the Verilog type checker, and should never be inputs.This removes the case that handles them as inputs.