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Verilog: cleanout unused Boolean operators from type checker #1290

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Oct 2, 2025
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Verilog: cleanout unused Boolean operators from type checker #1290

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11 changes: 8 additions & 3 deletions src/verilog/verilog_typecheck_expr.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3508,9 +3508,7 @@ exprt verilog_typecheck_exprt::convert_binary_expr(binary_exprt expr)

return std::move(expr);
}
else if(
expr.id() == ID_and || expr.id() == ID_or || expr.id() == ID_xor ||
expr.id() == ID_xnor || expr.id() == ID_nand || expr.id() == ID_nor)
else if(expr.id() == ID_and || expr.id() == ID_or)
{
for(auto &op : expr.operands())
{
Expand All @@ -3524,6 +3522,13 @@ exprt verilog_typecheck_exprt::convert_binary_expr(binary_exprt expr)

return std::move(expr);
}
else if(
expr.id() == ID_xor || expr.id() == ID_xnor || expr.id() == ID_nand ||
expr.id() == ID_nor)
{
// should not occur -- only generated by the typechecker
PRECONDITION(false);
}
Comment on lines +3525 to +3531
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The n_input_gatetype in the parser has all these - should the parser be changed as well, or am I misreading this?

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This is just the gate type, and doesn't turn into an expression before synthesis.

else if(expr.id() == ID_verilog_value_range)
{
for(auto &op : expr.operands())
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