Verilog: fix assignment for module output ports #640
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
kroening
force-pushed
the
verilog-instantiate-outputs
branch
from
33babed to
711ac42
Compare
This flips the assignments generated by synthesis for module output ports to read c := port for a connected signal c, instead of port := c.
kroening
force-pushed
the
verilog-instantiate-outputs
branch
from
711ac42 to
c9e0ee9
Compare
tautschnig
approved these changes
Aug 27, 2024
I am afraid not -- the order only becomes a problem with the changes in #639. |
Romy15200
pushed a commit
to Romy15200/nws
that referenced
this pull request
Aug 19, 2025
…puts Verilog: fix assignment for module output ports
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This flips the assignments generated by synthesis for module output ports to read
c := portfor a connected signal
c, instead ofport := c.