v0.5.10: Phase 5.5 Wave 2 -- IPI/SMP Foundation + PCI/PCIe Completion

VeridianOS v0.5.10 -- Phase 5.5 Wave 2: IPI/SMP Foundation + PCI/PCIe Completion

Date: February 27, 2026

Second Phase 5.5 Infrastructure Bridge release. Implements Wave 2 (multi-core coordination + modern device infrastructure) of the 12-sprint Phase 5.5 roadmap, providing IPI-based cross-CPU coordination and complete PCI/PCIe interrupt infrastructure required for future SMP scheduling, GPU drivers, and NVMe storage.

What's New

Sprint B-3: IPI + SMP Foundation

Inter-Processor Interrupt infrastructure for cross-CPU coordination:

• IPI vector constants: TLB_SHOOTDOWN_VECTOR = 49 for cross-CPU TLB invalidation, SCHED_WAKE_VECTOR = 50 for breaking idle CPUs out of HLT when tasks are enqueued.
• INIT-SIPI-SIPI AP startup: cpu_up() now sends proper Intel SDM AP startup sequence via APIC ICR (INIT IPI -> 10ms delay -> Startup IPI with trampoline page vector -> 200us delay -> retry SIPI if AP not online). Replaces previous stub implementation.
• LocalApic IPI methods: send_init_ipi() (INIT delivery mode), send_startup_ipi() (SIPI with page vector), send_ipi_all_excluding_self() (broadcast shorthand 0b11).
• IDT handlers: tlb_shootdown_handler at vector 49 flushes local TLB via CR3 reload + sends APIC EOI. sched_wake_handler at vector 50 acknowledges wake IPI with APIC EOI (scheduler picks up new tasks on next decision).
• TLB shootdown integration: TlbFlushBatch::flush_with_shootdown() performs local TLB flush followed by broadcast IPI to all other CPUs for cross-CPU page table invalidation.
• SMP IPI wiring: smp::send_ipi() x86_64 path now calls actual apic::send_ipi() via APIC ICR instead of println stub. apic::send_ipi() removed dead_code annotation.

Sprint B-4: PCI/PCIe Completion

Modern PCI interrupt and configuration infrastructure:

• MSI capability parsing: MsiCapability struct captures capability offset, 64-bit address support, per-vector masking, and maximum vector count (log2). Parsed from PCI capability chain (cap ID 0x05).
• MSI-X capability parsing: MsixCapability struct captures table size, table BAR/offset, and PBA BAR/offset. Parsed from PCI capability chain (cap ID 0x11).
• Capability chain walker: parse_capabilities() iterates PCI capabilities linked list starting at offset 0x34, with 48-iteration safety limit to prevent infinite loops on malformed hardware.
• PCI bridge enumeration: scan_bridge() recursively scans secondary buses behind PCI-to-PCI bridges. Bridge secondary bus number read from header type 1 offset 0x19. enumerate_devices() automatically detects bridges and recurses.
• MSI configuration: configure_msi() programs MSI message address (Intel format: 0xFEE00000 | dest_apic_id << 12) and message data (vector number) for interrupt delivery to target APIC. Supports both 32-bit and 64-bit address modes. Enables MSI via Message Control register.
• PCIe ECAM access: ecam_read_config() / ecam_write_config() provide memory-mapped PCI configuration space access using MCFG-provided base address from ACPI. Address formula: base + (bus << 20) + (device << 15) + (function << 12) + offset. x86_64 only, uses phys_to_virt() for bootloader physical memory mapping.

QEMU Boot Test Results

Architecture	Tests	BOOTOK	APIC Timer	PCI Devices
x86_64 (2048M)	29/29	2x BOOTOK	1000Hz, 62758 ticks/ms	6 devices
AArch64 (256M)	29/29	2x BOOTOK	N/A (x86_64 only)	N/A
RISC-V (256M)	29/29	BOOTOK	N/A (x86_64 only)	N/A

Build Verification

• All 3 architectures: zero errors, zero warnings
• cargo clippy -D warnings: clean on all 3 targets
• cargo fmt --check: clean

Files Changed

File	Change	Description
kernel/src/arch/x86_64/apic.rs	Modified (+73 lines)	IPI vectors 49/50, send_init_ipi, send_startup_ipi, send_ipi_all_excluding_self
kernel/src/arch/x86_64/idt.rs	Modified (+19 lines)	TLB shootdown handler (vector 49), scheduler wake handler (vector 50)
kernel/src/drivers/pci.rs	Modified (+289 lines)	MsiCapability, MsixCapability, parse_capabilities, scan_bridge, configure_msi, ECAM
kernel/src/mm/vas.rs	Modified (+23 lines)	TlbFlushBatch::flush_with_shootdown()
kernel/src/sched/smp.rs	Modified (+50/-20 lines)	APIC IPI wiring, INIT-SIPI-SIPI in cpu_up()
kernel/src/fs/mod.rs	Modified	Version bump in /etc/os-release
kernel/src/services/shell/commands.rs	Modified	Version bump in uname
Cargo.toml	Modified	Version 0.5.9 -> 0.5.10
CHANGELOG.md	Modified	v0.5.10 entry
README.md	Modified	Latest release, Phase 5.5 status
CLAUDE.md	Modified	Latest release, Phase 5.5 progress
docs/RELEASE-HISTORY.md	Modified	v0.5.10 entry
to-dos/PHASE5.5_TODO.md	Modified	B-3 + B-4 checked complete
to-dos/MASTER_TODO.md	Modified	Phase 5.5 ~33%

Stats: 15 files changed, +538 / -51 lines

Phase 5.5 Progress

Sprint	Status
B-1: ACPI Parser	COMPLETE (v0.5.9)
B-2: APIC Timer	COMPLETE (v0.5.9)
B-3: IPI/SMP	COMPLETE (v0.5.10)
B-4: PCI/PCIe	COMPLETE (v0.5.10)
B-5: DMA/IOMMU	Planned (v0.5.11)
B-6: Shared Mem/Unix Sockets	Planned (v0.5.11)
B-7: Lock-Free Paths	Planned (v0.5.11)
B-8 through B-12	Planned (v0.5.12-v0.5.13)

Full Changelog

v0.5.9...v0.5.10