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| 1 | +/* |
| 2 | + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 OR MIT |
| 5 | + */ |
| 6 | + |
| 7 | +#pragma once |
| 8 | + |
| 9 | +#define ETS_UNCACHED_ADDR(addr) (addr) |
| 10 | +#define ETS_CACHED_ADDR(addr) (addr) |
| 11 | + |
| 12 | +// Base register read/write macros |
| 13 | +#define REG_READ(_r) ({ \ |
| 14 | + (*(volatile uint32_t *)(_r)); \ |
| 15 | + }) |
| 16 | + |
| 17 | +#define REG_WRITE(_r, _v) do { \ |
| 18 | + (*(volatile uint32_t *)(_r)) = (_v); \ |
| 19 | + } while(0) |
| 20 | + |
| 21 | +// Bit manipulation macros |
| 22 | +#define REG_GET_BIT(_r, _b) ({ \ |
| 23 | + (REG_READ(_r) & (_b)); \ |
| 24 | + }) |
| 25 | + |
| 26 | +#define REG_SET_BIT(_r, _b) do { \ |
| 27 | + REG_WRITE(_r, REG_READ(_r) | (_b)); \ |
| 28 | + } while(0) |
| 29 | + |
| 30 | +#define REG_CLR_BIT(_r, _b) do { \ |
| 31 | + REG_WRITE(_r, REG_READ(_r) & (~(_b))); \ |
| 32 | + } while(0) |
| 33 | + |
| 34 | +#define REG_SET_BITS(_r, _b, _m) do { \ |
| 35 | + REG_WRITE(_r, (REG_READ(_r) & ~(_m)) | ((_b) & (_m))); \ |
| 36 | + } while(0) |
| 37 | + |
| 38 | +// Field manipulation macros |
| 39 | +#define REG_GET_FIELD(_r, _f) ({ \ |
| 40 | + ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ |
| 41 | + }) |
| 42 | + |
| 43 | +#define REG_SET_FIELD(_r, _f, _v) do { \ |
| 44 | + REG_WRITE(_r, (REG_READ(_r) & ~((_f##_V) << (_f##_S))) | (((_v) & (_f##_V)) << (_f##_S))); \ |
| 45 | + } while(0) |
| 46 | + |
| 47 | +// Value field manipulation macros |
| 48 | +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) |
| 49 | + |
| 50 | +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f)) >> (_f##_S)) |
| 51 | + |
| 52 | +#define VALUE_SET_FIELD(_r, _f, _v) ((_r) = ((_r) & ~((_f) << (_f##_S))) | ((_v) << (_f##_S))) |
| 53 | + |
| 54 | +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r) = ((_r) & ~(_f)) | ((_v) << (_f##_S))) |
| 55 | + |
| 56 | +// Field to value conversion macros |
| 57 | +#define FIELD_TO_VALUE(_f, _v) (((_v) & (_f)) << _f##_S) |
| 58 | + |
| 59 | +#define FIELD_TO_VALUE2(_f, _v) (((_v) << _f##_S) & (_f)) |
| 60 | + |
| 61 | +// Peripheral register macros |
| 62 | +#define READ_PERI_REG(addr) REG_READ(ETS_UNCACHED_ADDR(addr)) |
| 63 | + |
| 64 | +#define WRITE_PERI_REG(addr, val) REG_WRITE(ETS_UNCACHED_ADDR(addr), (uint32_t)(val)) |
| 65 | + |
| 66 | +#define CLEAR_PERI_REG_MASK(reg, mask) do { \ |
| 67 | + WRITE_PERI_REG(reg, READ_PERI_REG(reg) & (~(mask))); \ |
| 68 | + } while(0) |
| 69 | + |
| 70 | +#define SET_PERI_REG_MASK(reg, mask) do { \ |
| 71 | + WRITE_PERI_REG(reg, READ_PERI_REG(reg) | (mask)); \ |
| 72 | + } while(0) |
| 73 | + |
| 74 | +#define GET_PERI_REG_MASK(reg, mask) ({ \ |
| 75 | + (READ_PERI_REG(reg) & (mask)); \ |
| 76 | + }) |
| 77 | + |
| 78 | +#define GET_PERI_REG_BITS(reg, hipos, lowpos) ({ \ |
| 79 | + ((READ_PERI_REG(reg) >> (lowpos)) & ((1 << ((hipos) - (lowpos) + 1)) - 1)); \ |
| 80 | + }) |
| 81 | + |
| 82 | +#define SET_PERI_REG_BITS(reg, bit_map, value, shift) do { \ |
| 83 | + WRITE_PERI_REG(reg, (READ_PERI_REG(reg) & (~((bit_map) << (shift)))) | (((value) & (bit_map)) << (shift))); \ |
| 84 | + } while(0) |
| 85 | + |
| 86 | +#define GET_PERI_REG_BITS2(reg, mask, shift) ({ \ |
| 87 | + ((READ_PERI_REG(reg) >> (shift)) & (mask)); \ |
| 88 | + }) |
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