SIMD Support for PPC64LE

[Jenkins-J]

Hello,
I am curious what the state of SIMD support for ppc64le is in faiss. I did some searching and found this PR which appears to implement some functions to speed up execution on ppc64le (#3364). This does not seem to be a complete implementation of ppc64le SIMD operations for all faiss functions. For example, in CMakeLists.txt there is no ppc64le equivalent to FAISS_SIMD_AVX2_SRC and ppc64le does not have its own SIMDLevel:

faiss/faiss/impl/simdlib/simdlib.h

Line 54 in 3f08095

#include <faiss/impl/simdlib/simdlib_ppc64.h>

Any information is appreciated.
@carll99 @mdouze, any details on what the above PR covers and why it was created may also be helpful.

Thank you.

[Arthur031221]

ppc64le does not have its own SIMD level in faiss. It gets a hand-tuned scalar fallback, not vectorized SIMD, and that has not changed in the current release.

I checked this against faiss-cpu 1.15.1 (pip install faiss-cpu) and the matching v1.15.1 source tag.

faiss/utils/simd_levels.h enumerates every SIMD level the library knows about:

enum class SIMDLevel {
    NONE,
    AVX2,
    AVX512,
    AVX512_SPR,
    ARM_NEON,
    ARM_SVE,
    RISCV_RVV,
    AVX512_VPOPCNT,
    COUNT
};

There is no PPC64/VSX entry. faiss/impl/simdlib/simdlib.h says exactly why, right above the include that picks the fallback:

// NONE specialization: always included.
// Provides simd16uint16_tpl<NONE> etc. (scalar fallback).
// On PPC64: uses PPC-optimized scalar code (hand-tuned loop unrolling).
// Elsewhere: generic scalar implementation.
#if defined(__PPC64__)
#include <faiss/impl/simdlib/simdlib_ppc64.h>
#else
#include <faiss/impl/simdlib/simdlib_emulated.h>
#endif

So on ppc64le the "NONE" level is implemented by simdlib_ppc64.h instead of the generic emulated scalar code, but it is still the NONE level, with no SIMDLevel of its own. faiss/CMakeLists.txt backs this up: AVX2, AVX512 and NEON each get their own FAISS_SIMD_*_SRC source group, while impl/simdlib/simdlib_ppc64.h is just listed alongside the other plain headers with no equivalent group.

The PR you found, #3364, confirms what it actually did: the title is "Unroll loop in lookup_2_lanes," it touches only faiss/utils/simdlib.h and faiss/utils/simdlib_ppc64.h, and the description is explicit that it is manual loop unrolling to cut branch stalls in one function (lookup_2_lanes), measured as a 55% reduction on Power10 for bench_ivf_fastscan.py. That is a scalar-code optimization, not the start of a vectorized ppc64le backend using Altivec/VSX intrinsics.

So: the PR you found is the whole story, not a partial one. ppc64le gets the same NONE-level dispatch path as any unsupported architecture, with one function hand-unrolled for Power10, and no CMake-level SIMD source group or SIMDLevel entry exists for it.

[Jenkins-J]

Thank you @Arthur031221. This was very helpful!