Flexible Intermediate Representation for RTL
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jackkoenig Asynchronous Reset (#1011)
Fixes #219

* Adds AsyncResetType (similar to ClockType)
* Registers with reset signal of type AsyncResetType are async reset
* Registers with async reset can only be reset to literal values
* Add initialization logic for async reset registers
Latest commit 2272044 Feb 14, 2019
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.github Add CODEOWNERS file (#895) Sep 21, 2018
doc/images Add FIRRTL logo to repo and README (#938) Nov 13, 2018
notes WIP Jan 16, 2016
project Remove ghpages plugin (#996) Jan 22, 2019
regress Change primop arg type (#587) Feb 21, 2018
scripts Bump sbt (#703) Dec 18, 2017
spec Add MidFIRRTL spec (#1003) Jan 31, 2019
src Asynchronous Reset (#1011) Feb 14, 2019
test/integration Protobuf (#832) Jun 28, 2018
utils/bin Instance Annotations (#926) Oct 31, 2018
.fix_yosys_abc.patch Improve Travis configuration and revert Yosys version May 30, 2018
.gitignore WiringTransform Refactor (#648) Jan 15, 2018
.install_verilator.sh Bump version of Verilator used in Travis to 3.922 (#784) May 16, 2018
.install_yosys.sh Improve Travis configuration and revert Yosys version May 30, 2018
.run_chisel_tests.sh Fix TRAVIS_COMMIT_RANGE in .run_chisel_tests, replace ... with .. (#924) Oct 28, 2018
.run_formal_checks.sh API change: out-of-bounds vec accesses now invalid, not first element ( Dec 23, 2017
.travis.yml Fix $TRAVIS_COMMIT_RANGE (#927) Oct 31, 2018
Makefile Number all code examples & add specification build to Makefile (#894) Sep 27, 2018
README.md Update documentation links Dec 26, 2018
TODO WIP getting through tests Jan 16, 2016
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root-doc.txt Fix ScalaDoc complaints; add sbt-site, sbt-ghpages boilerplate. Jan 5, 2017
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Flexible Internal Representation for RTL

Firrtl is an intermediate representation (IR) for digital circuits designed as a platform for writing circuit-level transformations. This repository consists of a collection of transformations (written in Scala) which simplify, verify, transform, or emit their input circuit.

A Firrtl compiler is constructed by chaining together these transformations, then writing the final circuit to a file.

For a detailed description of Firrtl's intermediate representation, see the document "Specification of the Firrtl Language" located in spec/spec.pdf.

Wiki Pages and Tutorials

Useful information is on our wiki, located here:

Some important pages to read, before writing your own transform:

To write a Firrtl transform, please start with the tutorial here: src/main/scala/tutorial. To run these examples:

sbt assembly
./utils/bin/firrtl -td regress -tn rocket --custom-transforms tutorial.lesson1.AnalyzeCircuit
./utils/bin/firrtl -td regress -tn rocket --custom-transforms tutorial.lesson2.AnalyzeCircuit

Other Tools

Installation Instructions

Disclaimer: The installation instructions should work for OSX/Linux machines. Other environments may not be tested.

  1. If not already installed, install verilator (Requires at least v3.886)
  2. If not already installed, install sbt (Requires at least v0.13.6)
  1. Clone the repository: git clone https://github.com/freechipsproject/firrtl.git && cd firrtl
  2. Compile firrtl: sbt compile
  3. Run tests: sbt test
  4. Build executable (utils/bin/firrtl): sbt assembly
    • Note: You can add utils/bin to your path to call firrtl from other processes
  5. Publish this version locally in order to satisfy other tool chain library dependencies:
sbt publishLocal
Useful sbt Tips
  1. Run a single test suite: sbt "testOnly firrtlTests.UnitTests"
  2. Continually execute a command: sbt ~compile
  3. Only invoke sbt once:
> compile
> test
Using Firrtl as a commandline tool
utils/bin/firrtl -i regress/rocket.fir -o regress/rocket.v -X verilog // Compiles rocket-chip to Verilog
utils/bin/firrtl --help // Returns usage string
Citing Firrtl

If you use Firrtl in a paper, please cite the following ICCAD paper and technical report: https://ieeexplore.ieee.org/document/8203780

author={A. Izraelevitz and J. Koenig and P. Li and R. Lin and A. Wang and A. Magyar and D. Kim and C. Schmidt and C. Markley and J. Lawson and J. Bachrach}, 
booktitle={2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}, 
title={Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations}, 
keywords={field programmable gate arrays;hardware description languages;program compilers;software reusability;hardware development practices;hardware libraries;open-source hardware intermediate representation;hardware compiler transformations;Hardware construction languages;retargetable compilers;software development;virtual Cambrian explosion;hardware compiler frameworks;parameterized libraries;FIRRTL;FPGA mappings;Chisel;Flexible Intermediate Representation for RTL;Reusability;Hardware;Libraries;Hardware design languages;Field programmable gate arrays;Tools;Open source software;RTL;Design;FPGA;ASIC;Hardware;Modeling;Reusability;Hardware Design Language;Hardware Construction Language;Intermediate Representation;Compiler;Transformations;Chisel;FIRRTL}, 


    Author = {Li, Patrick S. and Izraelevitz, Adam M. and Bachrach, Jonathan},
    Title = {Specification for the FIRRTL Language},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {2016},
    Month = {Feb},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-9.html},
    Number = {UCB/EECS-2016-9}