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drm/i915: Rename intel_dkl_phy_reg to intel_hip_reg
Signed-off-by: Imre Deak <imre.deak@intel.com>
1 parent 10fbf2c commit e325c4d

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5 files changed

+92
-36
lines changed

5 files changed

+92
-36
lines changed

‎drivers/gpu/drm/i915/display/intel_dkl_phy.c‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88

99
#include "intel_de.h"
1010
#include "intel_display.h"
11-
#include "intel_dkl_phy.h"
11+
#include "intel_hip_reg.h"
1212

1313
/*
1414
* Each HIP register segment is addressed through a 4KB aperture window. Each segment
@@ -34,7 +34,7 @@ void intel_hip_reg_init(struct intel_display *display)
3434
}
3535

3636
static void
37-
hip_reg_set_bank_idx(struct intel_display *display, struct intel_dkl_phy_reg reg)
37+
hip_reg_set_bank_idx(struct intel_display *display, struct intel_hip_reg reg)
3838
{
3939
int seg_idx = HIP_REG_SEG_IDX(reg);
4040

@@ -48,83 +48,83 @@ hip_reg_set_bank_idx(struct intel_display *display, struct intel_dkl_phy_reg reg
4848
}
4949

5050
/**
51-
* intel_dkl_phy_read - read a Dekel PHY register
51+
* intel_hip_reg_read - read a HIP register
5252
* @display: intel_display device instance
53-
* @reg: Dekel PHY register
53+
* @reg: HIP register
5454
*
55-
* Read the @reg Dekel PHY register.
55+
* Read the @reg HIP register.
5656
*
5757
* Returns the read value.
5858
*/
5959
u32
60-
intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
60+
intel_hip_reg_read(struct intel_display *display, struct intel_hip_reg reg)
6161
{
6262
u32 val;
6363

6464
spin_lock(&display->hip_reg.lock);
6565

6666
hip_reg_set_bank_idx(display, reg);
67-
val = intel_de_read(display, DKL_REG_MMIO(reg));
67+
val = intel_de_read(display, HIP_REG_MMIO(reg));
6868

6969
spin_unlock(&display->hip_reg.lock);
7070

7171
return val;
7272
}
7373

7474
/**
75-
* intel_dkl_phy_write - write a Dekel PHY register
75+
* intel_hip_reg_write - write a HIP register
7676
* @display: intel_display device instance
77-
* @reg: Dekel PHY register
77+
* @reg: HIP register
7878
* @val: value to write
7979
*
80-
* Write @val to the @reg Dekel PHY register.
80+
* Write @val to the @reg HIP register.
8181
*/
8282
void
83-
intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val)
83+
intel_hip_reg_write(struct intel_display *display, struct intel_hip_reg reg, u32 val)
8484
{
8585
spin_lock(&display->hip_reg.lock);
8686

8787
hip_reg_set_bank_idx(display, reg);
88-
intel_de_write(display, DKL_REG_MMIO(reg), val);
88+
intel_de_write(display, HIP_REG_MMIO(reg), val);
8989

9090
spin_unlock(&display->hip_reg.lock);
9191
}
9292

9393
/**
94-
* intel_dkl_phy_rmw - read-modify-write a Dekel PHY register
94+
* intel_hip_reg_rmw - read-modify-write a HIP register
9595
* @display: display device instance
96-
* @reg: Dekel PHY register
96+
* @reg: HIP register
9797
* @clear: mask to clear
9898
* @set: mask to set
9999
*
100-
* Read the @reg Dekel PHY register, clearing then setting the @clear/@set bits in it, and writing
100+
* Read the @reg HIP register, clearing then setting the @clear/@set bits in it, and writing
101101
* this value back to the register if the value differs from the read one.
102102
*/
103103
void
104-
intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set)
104+
intel_hip_reg_rmw(struct intel_display *display, struct intel_hip_reg reg, u32 clear, u32 set)
105105
{
106106
spin_lock(&display->hip_reg.lock);
107107

108108
hip_reg_set_bank_idx(display, reg);
109-
intel_de_rmw(display, DKL_REG_MMIO(reg), clear, set);
109+
intel_de_rmw(display, HIP_REG_MMIO(reg), clear, set);
110110

111111
spin_unlock(&display->hip_reg.lock);
112112
}
113113

114114
/**
115-
* intel_dkl_phy_posting_read - do a posting read from a Dekel PHY register
115+
* intel_hip_reg_posting_read - do a posting read from a HIP register
116116
* @display: display device instance
117-
* @reg: Dekel PHY register
117+
* @reg: HIP register
118118
*
119-
* Read the @reg Dekel PHY register without returning the read value.
119+
* Read the @reg HIP register without returning the read value.
120120
*/
121121
void
122-
intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
122+
intel_hip_reg_posting_read(struct intel_display *display, struct intel_hip_reg reg)
123123
{
124124
spin_lock(&display->hip_reg.lock);
125125

126126
hip_reg_set_bank_idx(display, reg);
127-
intel_de_posting_read(display, DKL_REG_MMIO(reg));
127+
intel_de_posting_read(display, HIP_REG_MMIO(reg));
128128

129129
spin_unlock(&display->hip_reg.lock);
130130
}

‎drivers/gpu/drm/i915/display/intel_dkl_phy.h‎

Lines changed: 29 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -9,17 +9,37 @@
99
#include <linux/types.h>
1010

1111
#include "intel_dkl_phy_regs.h"
12+
#include "intel_hip_reg.h"
1213

1314
struct intel_display;
1415

15-
void intel_hip_reg_init(struct intel_display *display);
16-
u32
17-
intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg);
18-
void
19-
intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val);
20-
void
21-
intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set);
22-
void
23-
intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg);
16+
static inline struct intel_hip_reg dkl_phy_to_hip_reg(struct intel_dkl_phy_reg reg)
17+
{
18+
return (const struct intel_hip_reg){ .reg = reg.reg, .bank_idx = reg.bank_idx };
19+
}
20+
21+
static inline u32
22+
intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
23+
{
24+
return intel_hip_reg_read(display, dkl_phy_to_hip_reg(reg));
25+
}
26+
27+
static inline void
28+
intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val)
29+
{
30+
intel_hip_reg_write(display, dkl_phy_to_hip_reg(reg), val);
31+
}
32+
33+
static inline void
34+
intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set)
35+
{
36+
intel_hip_reg_rmw(display, dkl_phy_to_hip_reg(reg), clear, set);
37+
}
38+
39+
static inline void
40+
intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
41+
{
42+
intel_hip_reg_posting_read(display, dkl_phy_to_hip_reg(reg));
43+
}
2444

2545
#endif /* __INTEL_DKL_PHY_H__ */

‎drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,17 @@
1010

1111
#include "intel_hip_reg_defs.h"
1212

13+
struct intel_dkl_phy_reg {
14+
u32 reg:24;
15+
u32 bank_idx:4;
16+
};
17+
18+
#define _DKL_REG(tc_port, offset) ({ \
19+
struct intel_hip_reg hr = HIP_REG(tc_port, offset); \
20+
struct intel_dkl_phy_reg dr = { hr.reg, hr.bank_idx }; \
21+
dr; \
22+
})
23+
1324
#define _DKL_REG_LN(tc_port, ln_idx, ln0_offs, ln1_offs) \
1425
_DKL_REG(tc_port, (ln0_offs) + (ln_idx) * ((ln1_offs) - (ln0_offs)))
1526

‎drivers/gpu/drm/i915/display/intel_hip_reg.h‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
/* SPDX-License-Identifier: MIT */
2+
/*
3+
* Copyright © 2025 Intel Corporation
4+
*/
5+
6+
#ifndef __INTEL_HIP_REG_H__
7+
#define __INTEL_HIP_REG_H__
8+
9+
#include <linux/types.h>
10+
11+
#include "intel_hip_reg_defs.h"
12+
13+
struct intel_display;
14+
15+
void intel_hip_reg_init(struct intel_display *display);
16+
u32
17+
intel_hip_reg_read(struct intel_display *display, struct intel_hip_reg reg);
18+
void
19+
intel_hip_reg_write(struct intel_display *display, struct intel_hip_reg reg, u32 val);
20+
void
21+
intel_hip_reg_rmw(struct intel_display *display, struct intel_hip_reg reg, u32 clear, u32 set);
22+
void
23+
intel_hip_reg_posting_read(struct intel_display *display, struct intel_hip_reg reg);
24+
25+
#endif /* __INTEL_HIP_REG_H__ */

‎drivers/gpu/drm/i915/display/intel_hip_reg_defs.h‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010

1111
#include "intel_display_reg_defs.h"
1212

13-
struct intel_dkl_phy_reg {
13+
struct intel_hip_reg {
1414
u32 reg:24;
1515
u32 bank_idx:4;
1616
};
@@ -20,8 +20,8 @@ struct intel_dkl_phy_reg {
2020

2121
#define HIP_REG_SEG_NUM 8
2222

23-
/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
24-
#define DKL_REG_MMIO(__reg) _MMIO((__reg).reg)
23+
/* HIP REG MMIO Address = HIP segment base + (internal address & ~segment_index_mask) */
24+
#define HIP_REG_MMIO(__reg) _MMIO((__reg).reg)
2525

2626
#define HIP_REG_SEG_IDX(__reg) \
2727
(((__reg).reg - _HIP_REG_SEG0_BASE) / (_HIP_REG_SEG1_BASE - _HIP_REG_SEG0_BASE))
@@ -37,8 +37,8 @@ struct intel_dkl_phy_reg {
3737
#define _HIP_REG_SEG_BANK_IDX(__offset) \
3838
(((__offset) >> _HIP_REG_SEG_BANK_SHIFT) & 0xf)
3939

40-
#define _DKL_REG(__seg_idx, __seg_offset) \
41-
((const struct intel_dkl_phy_reg) { \
40+
#define HIP_REG(__seg_idx, __seg_offset) \
41+
((const struct intel_hip_reg) { \
4242
.reg = _HIP_REG_SEG_BASE(__seg_idx) + \
4343
_HIP_REG_SEG_BANK_OFFSET(__seg_offset), \
4444
.bank_idx = _HIP_REG_SEG_BANK_IDX(__seg_offset), \

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