Run Verilog/SystemVerilog testbench with Icarus Verilog and GTKWave support.
The extension need Verilog and SystemVerilog filetypes registry in VSCode, the easy way is to install previously the extension mshr-h.veriloghdl from VS Code Marketplace or Open VSX Registry that includes HDL support for VS Code with Syntax Highlighting, Snippets, Linting, Formatting, etc.
Also it is necessary to install Icarus Verilog and GTKWave tools, and be sure that iverilog and gtkwave have beebn added to your environment PATH variable.
If you need help, check out the installation guide for Windows and other OSes.
The extension adds in VSCode:
- two buttons in the titlebar of any Verilog/SystemVerilog file:
- Run testbench simulation
- Stop simulation and clean build files
- a status item positioned in the lower-right corner
- console log output of commands and running testbench
verilog.gtkwaveWatchGlob: GTKWave will be launched when a file relative to the build directory satisfy this glob (VCD files).verilog.icarusCompileArguments: Arguments passed to Verilog compiler (see Icarus Verilog documentation).verilog.icarusBuildDirectory: Build folder path relative to workspace root (recommended).verilog.icarusPersistentBuild: True if build folder should not be cleared before each compilation.
The extension code is licensed under MIT.
This extension began as a fork of Verilog Testbench Runner theonekevin.icarusext in order to include support for SystemVerilog files and automate GTKWave launch.
Acknowledgments to Kevin Dai.