Quick demo for Lattice FPGA with RiscV, Based on Trenz CR00103-03 Certus-NX board.
FPGA based RiscV, based on the out-of-the-box 'hello world' template from Lattice.
More info to be found on the following
- Trenz Cruvi Board
- Example1 - not the best example, but its a start.
- Example2 - a bit more details but based on other board.
- Propel Tools video @ Lattice - MUST SEE !
- Lattice Certus-NX
Code Content is the Propel Builder (verilog project) and the Propel SDK code (C-project)
Lattice currently is pretty lean on the base templates for propel and RiscV. This project is a try out and adds an I2C master port.
C-Code is added to drive an AdaFruit PiOled display of 128x32 pixels to show the concept.
Follow the Lattice Propel Video's to understand the work-flow for designing a RiscV on FPGA.
Key is to add the post-constain file to constain the IO pins of the RX/TX and SCL/SDA pins, and add the sysmem initialisation to your C-code mem-file.
Propel is license free, but you do need to apply for a free license via their website after registration.