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This repository has been archived by the owner on Feb 5, 2023. It is now read-only.
diff --git a/cores/track/hdl/jttrack_main.v b/cores/track/hdl/jttrack_main.v
index 5264d4b..0ada954 100644
--- a/cores/track/hdl/jttrack_main.v
+++ b/cores/track/hdl/jttrack_main.v
@@ -78,14 +78,12 @@ reg irq_clrn, ram_cs;
reg ior_cs, in5_cs,
iow_cs;
wire VMA;
-reg nvram_we;
+wire nvram_we;
assign irq_trigger = ~LVBL & dip_pause;
assign cpu_rnw = RnW;
assign rom_addr = A;
-
-always @(posedge clk)
- nvram_we <= ioctl_ram && ioctl_wr && ioctl_addr[15:11]==0;
+assign nvram_we = ioctl_ram && ioctl_wr && ioctl_addr[15:11]==0;
always @(*) begin
// the ROM logic has some optional jumpers and the PCB we got
Sorry, no PR, but the fix is really trivial - nvram_we's clock is wrong, it should be the same as dma_clk(clk48). However I think it's even better to not delay this signal in respect to ioctl_wr - thus use combinatorial logic.
The text was updated successfully, but these errors were encountered:
Fortunately easy to fix:
Sorry, no PR, but the fix is really trivial - nvram_we's clock is wrong, it should be the same as dma_clk(clk48). However I think it's even better to not delay this signal in respect to ioctl_wr - thus use combinatorial logic.
The text was updated successfully, but these errors were encountered: