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I build my own little RISC orientated processor in VHDL with Quartus

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db
db
 
 
greybox_tmp
greybox_tmp
 
 
incremental_db/compiled_partitions
incremental_db/compiled_partitions
 
 
output_files
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simulation/modelsim
simulation/modelsim
 
 
HEX_IO.vhd
HEX_IO.vhd
 
 
HEX_IO.vhd.bak
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LED_IO.vhd
LED_IO.vhd
 
 
MIFRAM.vhd
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README.md
README.md
 
 
SCA.mif
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SCA.qsf
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SCA.vhd
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SCAMIF.mif
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SCA_nativelink_simulation.rpt
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SCA_types.vhd
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SCA_types.vhd.bak
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SmallComputerArchitecture.qpf
SmallComputerArchitecture.qpf
 
 
address_decoder.vhd
address_decoder.vhd
 
 
assignment_defaults.qdf
assignment_defaults.qdf
 
 
control_unit_2.vhd
control_unit_2.vhd
 
 
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convDisp7.vhd
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convDisp7.vhd.bak
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dBus2Pcr_MUX.vhd
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key_IO.vhd
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memory.vhd
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memory.vhd.bak
memory.vhd.bak
 
 
processor.zip
processor.zip
 
 
single_port_ram_mega_function.cmp
single_port_ram_mega_function.cmp
 
 
single_port_ram_mega_function.qip
single_port_ram_mega_function.qip
 
 
single_port_ram_mega_function.qip.bak
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single_port_ram_mega_function.vhd
single_port_ram_mega_function.vhd
 
 
single_port_ram_with_init.vhd
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single_port_ram_with_init.vhd.bak
 
 
testKeys.vwf
testKeys.vwf
 
 
testMem.vwf
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test_tb.vhd
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top_Mem_DE0.vhd
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top_SCA_DE0.vhd
top_SCA_DE0.vhd
 
 
toy_XFSA.vhd
toy_XFSA.vhd
 
 

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This is my own designed RISC architecture processor. I will provide a documentation about my instruction set (MNEMONICS) and a design of my architecture soon.

The processor is written in VHDL using Quartus.

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I build my own little RISC orientated processor in VHDL with Quartus

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fpga processor vhdl riscv risc quartus

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