v0.8.0

someda 0.8.0: the desktop app (someda-app) over the engine

v0.7.0

someda 0.7.0: differential pairs, enforced crosstalk spacing, oscilla…

someda 0.6.1

someda 0.6.1 — real footprints, 2/4/6-layer routing, silk-clean, formulas cross-checked

Built from branch feat/multilayer-real-footprints (PR #1). Every item below was verified against kicad-cli 10.0.6 on real boards.

Footprints

• footprint: "Lib:Name" resolves to the installed KiCad .kicad_mod (plus SOMEDA_FOOTPRINT_DIRS), embedded verbatim with placement, reference and pad nets injected. Pin coverage is checked against the footprint's real pad numbers.
• Footprint rotation corrected to KiCad's convention: 130/130 rotated pads on tests/corpus/interf_u match kicad-cli's IPC-D-356 export (the old transform matched 0/130).

Layers, planes, rules

• layers 2/4/6 (up to 12), full technical layer table, zones on inner layers with regions, priority and "auto" islands.
• JLCPCB stackup presets per layer count; a .kicad_pro written next to the board so kicad-cli judges by the fab rules (0.127/0.127 mm, 0.35/0.20 mm vias on multilayer) instead of its 0.2 mm defaults.

Placement

• Courtyard-aware: connectors flush to their edge at an edge_at slot with rotation, parts next to the pins they share a net with (near), keep-out ring around fine-pitch ICs, thermal keep-apart, no overlaps.

Router

• Dense occupancy over every signal layer; real rotated pad rectangles (circles as ellipses); through-hole pads block every layer; hole clearance; footprint keep-out zones.
• Plane fanout per pad (sites under the body preferred) with trace fallback; depth-staggered escape vias for every fine-pitch signal pin; escape lanes and bands that keep other nets and wide traces out of pin rows.
• Route-to-net via union-find components, whole-net rip-up-and-reroute plus final retries, collinear segment merging.

Honest gates

• The kicad-cli DRC stage parses the report file: errors and unconnected items fail, warnings are listed. (0.5.x passed boards with unconnected pads.)
• Gerber set for every copper layer plus mask/paste/silk/outline with zones checked, drill map, position file, BOM, top/bottom PNG renders.
• Engine DRC and ERC judge by the board's rules; the schematic parser matches symbols by full name.

Checkpoints

Board	0.5.4	0.6.0
7-part 555 example (README)	NOT DONE, 2–5 unrouted	13/13 routed, DRC 0 errors, 6/6 gates
26-part 6-layer LQFP-48 board	—	31/31 routed, DRC 0 errors, 6/6 gates
132-part Allwinner V3s SBC (plugin examples/sompi-v3s)	—	192/192 routed, 220 plane fanouts, 130 escape vias, DRC 0 errors, 13 Gerber layers

Not in this release

Differential-pair routing and length matching (pairs are two single-ended traces), bottom-side placement, electrical simulation, a Linux arm64 asset (the plugin's setup script builds from source there).

0.6.1 on top of 0.6.0

• Silkscreen never touches a pad: references placed clear of other parts or moved to F.Fab; Gerber silk subtracted by the solder mask; silk, courtyard, keep-out, connection-width and mask-bridge findings fail the DRC gate.
• Microstrip Z0 is Hammerstad–Jensen (the 0.6.0 form went negative on thin dielectrics); the 6-layer 50 Ω width carries JLCPCB's calculator value with provenance; via loop inductance constant corrected; current-capacity function documented as IPC-2221. Tests assert against independent references; cargo run --example formula_probe prints every formula.
• Unused escape vias are kept and reported.
• The Linux x86_64 asset on this release was built from master 40b928f with cargo build --release --locked on the author's machine; the other platforms come from the Release workflow.

v0.6.0

someda 0.6.0: real KiCad footprints, 2/4/6-layer routing with planes …

v0.5.4

fix: v0.5.4 — pos export file target + env-only gate classification

Plugin-conversion E2E surfaced three gate-fidelity issues:

- kicad-cli 10's pos export takes an OUTPUT FILE (exit 4 on a
  directory) — the orchestrator now writes fab/positions.csv
  explicitly with --format csv
- kicad-cli erc/drc exit 5 fires even when the only findings are
  missing-library environment warnings — the wrapper classifies
  env-only results (lib_symbol_issues / lib_footprint_issues) as
  success with an explicit env-only note; real findings still fail
- someda's own gates annotate known limitations instead of failing:
  missing-power-flag is the documented M4 power-symbol gap,
  segment-check-truncation is the documented M2 spatial-index gap —
  both stay visible in the stage detail, neither blocks the verdict.
  Real findings (floating pins, decoupling, shorts, clearance) still
  fail the gate.

E2E via the plugin flow (Claude-planned 555 blinker with decoupling):
routed 561/561, all stages ✓, honest-done: VERIFIED, fab/ contains
Gerbers + drill + positions + BOM.

154/154 tests.

v0.5.3

test: v0.5.3 — authority locked: pin transform at all 4 rotations + K…

v0.5.2

fix: v0.5.2 — KiCad pin-transform authority + net-derivation fidelity…

v0.5.1

fix: v0.5.1 — physics validation round (stackup / L'C' identity / JLC…

v0.5.0

feat: v0.5.0 — physics-aware design harness (frequency / SI / thermal…

v0.4.3

fix: v0.4.3 — router geometry hardening (stress-topology validation r…