v0.5.1 — EJTAG-AXI streaming read, Vivado-free FTDI flow

fpgacapZero 0.5.1 is on PyPI: pip install -U fpgacapzero.

Highlights

EJTAG-AXI streaming read. One long JTAG scan now carries up to 16383 words, so the
cable sets the speed instead of per-scan tool overhead. On the Arty A7 at 30 MHz TCK:
about 2.8 MB/s over the FTDI backend and 1.9 MB/s over hw_server, up from 6 KB/s for
read_block over hw_server. Build the core with STREAM_EN=1 (Verilog only for now;
the default is off), then call EjtagAxiController.stream_read().

Program 7-series FPGAs over FTDI. --backend ftdi --program design.bit loads a
Vivado .bit or raw .bin over JTAG on the board's own cable, with no Vivado or
hw_server. The Arty A7 programs in 1.2 s. A bitstream built for another part is
refused before anything is erased. It also works from RPC, MCP and the desktop GUI.

Arty A7 hardware suite without Vivado. FPGACAP_BACKEND=ftdi runs the full Arty
hardware suite over the onboard cable: it programs the board itself, and all 71 tests
pass in about 25 s.

Also new

• FTDI backend samples TDO on the falling edge above 15 MHz, so 30 MHz TCK works on
  the Arty's onboard cable.
• fcapz openocd-bridge lets OpenOCD use FlashPro5 and Digilent cables on Windows
  without swapping their driver, so Libero and Vivado keep working.
• The MCP server can connect over ftdi and serial.
• New transport calls raw_dr_capture() and jtag_lock()/jtag_unlock().
• FTDI cancel() returns at once instead of waiting for the call it stops.

Fixes

• EJTAG-AXI: read data arriving after a timeout or RESET could be returned as
  the next read's result. The bridge now discards it (Verilog and VHDL).
• EJTAG-AXI (Verilog): a TIMEOUT above 4096 never fired, so a slave that never
  answered hung the bridge.
• UltraScale: the USER opcode table was wrong for single-die parts. On
  hw_server, UltraScale(+) parts now also work in multi-die configurations.
• Repeated connect(): calling it a second time no longer leaks the previous
  hw_server, OpenOCD or serial session.
• Cores built with USER1_DATA_EN=0: a capture that had to fall back to the
  data window used to return made-up zeros. It now raises DataWindowError.
• Manual: a full review against the code corrected claims in most chapters.
  A new CI check fails when doc examples drift from the code.

Changes to note

• The desktop GUI (fcapz-gui) still ships but is no longer actively developed.
  Use the web interface (fcapz-web) instead.
• RPC side connections for EIO, AXI and UART now ignore program; only the main
  session connect programs the FPGA.

The full list is in CHANGELOG.md.