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[CIR][CIRGen] Generate CIR for vset_lane and vsetq_lane intrinsics #882

Merged

bcardosolopes merged 2 commits into llvm:main from ghehg:macM3

Sep 24, 2024

Collaborator

ghehg commented Sep 24, 2024

As title.
Notice that for those intrinsics, just like OG, we do not lower to llvm intrinsics, instead, do vector insert.
The test case is partially from OG aarch64-neon-vget.c
But, I did not do all signed and unsigned int tests because unsigned and signed of the same width essentially just use the same intrinsic ID thus exactly same code path as far as this PR concerns.
I chose name aarch64-neon-vset.c as I intend to separate tests of vget_lane and vgetq_lane intrinsics into a different file
called aarch64-neon-vget.c( IMHO, it's better).


          Generate CIR for vset_lane and vsetq_lane intrinsics

55f5492

ghehg requested review from lanza and bcardosolopes as code owners

September 24, 2024 20:03

bcardosolopes approved these changes

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bcardosolopes left a comment

Awesome, LGTM


          comments in the test

66982c0

bcardosolopes merged commit a76cb16 into llvm:main

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ghehg mentioned this pull request

[CIR][CIRGen] Generate CIR for neon_vget and neon_vdup lane intrinsics #884

Merged

bcardosolopes pushed a commit that referenced this pull request


          [CIR][CIRGen] Generate CIR for neon_vget and neon_vdup lane intrinsics (

37aafef

#884)

as title. 
This PR has simliar test case organization as to
[PR882](#882)
Notice that comparing to OG, this PR combines cases for some pairs of
intrinsics such as
BI__builtin_neon_vget_lane_f32 and BI__builtin_neon_vdups_lane_f32. 
They have the same code generated in OG and CIRGen
OG separate them into different case handling because it passes
mnemonics which are different. CIRGen doesn't pass that so why not
combine them.

Co-authored-by: Guojin He <guojinhe@meta.com>

Hugobros3 pushed a commit to shady-gang/clangir that referenced this pull request


          [CIR][CIRGen] Generate CIR for vset_lane and vsetq_lane intrinsics (l…

…lvm#882)

As title. 
Notice that for those intrinsics, just like OG, we do not lower to llvm
intrinsics, instead, do vector insert.
The test case is partially from OG
[aarch64-neon-vget.c](https://github.com/llvm/clangir/blob/85bc6407f559221afebe08a60ed2b50bf1edf7fa/clang/test/CodeGen/aarch64-neon-vget.c)
But, I did not do all signed and unsigned int tests because unsigned and
signed of the same width essentially just use the same intrinsic ID thus
exactly same code path as far as this PR concerns.

---------

Co-authored-by: Guojin He <guojinhe@meta.com>

Hugobros3 pushed a commit to shady-gang/clangir that referenced this pull request


          [CIR][CIRGen] Generate CIR for neon_vget and neon_vdup lane intrinsics (

30a1a8e

llvm#884)

as title. 
This PR has simliar test case organization as to
[PR882](llvm#882)
Notice that comparing to OG, this PR combines cases for some pairs of
intrinsics such as
BI__builtin_neon_vget_lane_f32 and BI__builtin_neon_vdups_lane_f32. 
They have the same code generated in OG and CIRGen
OG separate them into different case handling because it passes
mnemonics which are different. CIRGen doesn't pass that so why not
combine them.

Co-authored-by: Guojin He <guojinhe@meta.com>

smeenai pushed a commit to smeenai/clangir that referenced this pull request


          [CIR][CIRGen] Generate CIR for vset_lane and vsetq_lane intrinsics (l…

b18d38d

…lvm#882)

As title. 
Notice that for those intrinsics, just like OG, we do not lower to llvm
intrinsics, instead, do vector insert.
The test case is partially from OG
[aarch64-neon-vget.c](https://github.com/llvm/clangir/blob/85bc6407f559221afebe08a60ed2b50bf1edf7fa/clang/test/CodeGen/aarch64-neon-vget.c)
But, I did not do all signed and unsigned int tests because unsigned and
signed of the same width essentially just use the same intrinsic ID thus
exactly same code path as far as this PR concerns.

---------

Co-authored-by: Guojin He <guojinhe@meta.com>

smeenai pushed a commit to smeenai/clangir that referenced this pull request


          [CIR][CIRGen] Generate CIR for neon_vget and neon_vdup lane intrinsics (

3df66bf

llvm#884)

as title. 
This PR has simliar test case organization as to
[PR882](llvm#882)
Notice that comparing to OG, this PR combines cases for some pairs of
intrinsics such as
BI__builtin_neon_vget_lane_f32 and BI__builtin_neon_vdups_lane_f32. 
They have the same code generated in OG and CIRGen
OG separate them into different case handling because it passes
mnemonics which are different. CIRGen doesn't pass that so why not
combine them.

Co-authored-by: Guojin He <guojinhe@meta.com>

smeenai pushed a commit to smeenai/clangir that referenced this pull request


          [CIR][CIRGen] Generate CIR for vset_lane and vsetq_lane intrinsics (l…

5b49794

…lvm#882)

As title. 
Notice that for those intrinsics, just like OG, we do not lower to llvm
intrinsics, instead, do vector insert.
The test case is partially from OG
[aarch64-neon-vget.c](https://github.com/llvm/clangir/blob/85bc6407f559221afebe08a60ed2b50bf1edf7fa/clang/test/CodeGen/aarch64-neon-vget.c)
But, I did not do all signed and unsigned int tests because unsigned and
signed of the same width essentially just use the same intrinsic ID thus
exactly same code path as far as this PR concerns.

---------

Co-authored-by: Guojin He <guojinhe@meta.com>

smeenai pushed a commit to smeenai/clangir that referenced this pull request


          [CIR][CIRGen] Generate CIR for neon_vget and neon_vdup lane intrinsics (

3e040c0

llvm#884)

as title. 
This PR has simliar test case organization as to
[PR882](llvm#882)
Notice that comparing to OG, this PR combines cases for some pairs of
intrinsics such as
BI__builtin_neon_vget_lane_f32 and BI__builtin_neon_vdups_lane_f32. 
They have the same code generated in OG and CIRGen
OG separate them into different case handling because it passes
mnemonics which are different. CIRGen doesn't pass that so why not
combine them.

Co-authored-by: Guojin He <guojinhe@meta.com>

smeenai pushed a commit to smeenai/clangir that referenced this pull request


          [CIR][CIRGen] Generate CIR for vset_lane and vsetq_lane intrinsics (l…

8595aa8

…lvm#882)

As title. 
Notice that for those intrinsics, just like OG, we do not lower to llvm
intrinsics, instead, do vector insert.
The test case is partially from OG
[aarch64-neon-vget.c](https://github.com/llvm/clangir/blob/85bc6407f559221afebe08a60ed2b50bf1edf7fa/clang/test/CodeGen/aarch64-neon-vget.c)
But, I did not do all signed and unsigned int tests because unsigned and
signed of the same width essentially just use the same intrinsic ID thus
exactly same code path as far as this PR concerns.

---------

Co-authored-by: Guojin He <guojinhe@meta.com>

smeenai pushed a commit to smeenai/clangir that referenced this pull request


          [CIR][CIRGen] Generate CIR for neon_vget and neon_vdup lane intrinsics (

69e7228

llvm#884)

as title. 
This PR has simliar test case organization as to
[PR882](llvm#882)
Notice that comparing to OG, this PR combines cases for some pairs of
intrinsics such as
BI__builtin_neon_vget_lane_f32 and BI__builtin_neon_vdups_lane_f32. 
They have the same code generated in OG and CIRGen
OG separate them into different case handling because it passes
mnemonics which are different. CIRGen doesn't pass that so why not
combine them.

Co-authored-by: Guojin He <guojinhe@meta.com>

keryell pushed a commit to keryell/clangir that referenced this pull request


          [CIR][CIRGen] Generate CIR for vset_lane and vsetq_lane intrinsics (l…

669eaa9

…lvm#882)

As title. 
Notice that for those intrinsics, just like OG, we do not lower to llvm
intrinsics, instead, do vector insert.
The test case is partially from OG
[aarch64-neon-vget.c](https://github.com/llvm/clangir/blob/85bc6407f559221afebe08a60ed2b50bf1edf7fa/clang/test/CodeGen/aarch64-neon-vget.c)
But, I did not do all signed and unsigned int tests because unsigned and
signed of the same width essentially just use the same intrinsic ID thus
exactly same code path as far as this PR concerns.

---------

Co-authored-by: Guojin He <guojinhe@meta.com>

keryell pushed a commit to keryell/clangir that referenced this pull request


          [CIR][CIRGen] Generate CIR for neon_vget and neon_vdup lane intrinsics (

98586db

llvm#884)

as title. 
This PR has simliar test case organization as to
[PR882](llvm#882)
Notice that comparing to OG, this PR combines cases for some pairs of
intrinsics such as
BI__builtin_neon_vget_lane_f32 and BI__builtin_neon_vdups_lane_f32. 
They have the same code generated in OG and CIRGen
OG separate them into different case handling because it passes
mnemonics which are different. CIRGen doesn't pass that so why not
combine them.

Co-authored-by: Guojin He <guojinhe@meta.com>

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