[CIR][CIRGen] Generate CIR for neon_vget and neon_vdup lane intrinsics #884
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| // CIR: [[IDX:%.*]] = cir.const #cir.int<15> : !s32i | ||
| // CIR: {{%.*}} = cir.vec.extract {{%.*}}[[[IDX]] : !s32i] : !cir.vector<!u8i x 16> | ||
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| // LLVM: define dso_local i8 @test_vdupb_laneq_s8(<16 x i8> [[ARG:%.*]]) |
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For new rounds, might be a good idea to use LLVM-LABEL or remove the extra details (like dso_local), just so that if more of those unrelated things get added it won't require us to change these tests.
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Sure, I added the full check simply because I want to have [[ARG:%.*]] so I know intrinsic argument is from the function argument. But maybe there is another way to achieve it.
Hugobros3
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llvm#884) as title. This PR has simliar test case organization as to [PR882](llvm#882) Notice that comparing to OG, this PR combines cases for some pairs of intrinsics such as BI__builtin_neon_vget_lane_f32 and BI__builtin_neon_vdups_lane_f32. They have the same code generated in OG and CIRGen OG separate them into different case handling because it passes mnemonics which are different. CIRGen doesn't pass that so why not combine them. Co-authored-by: Guojin He <guojinhe@meta.com>
smeenai
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Oct 9, 2024
llvm#884) as title. This PR has simliar test case organization as to [PR882](llvm#882) Notice that comparing to OG, this PR combines cases for some pairs of intrinsics such as BI__builtin_neon_vget_lane_f32 and BI__builtin_neon_vdups_lane_f32. They have the same code generated in OG and CIRGen OG separate them into different case handling because it passes mnemonics which are different. CIRGen doesn't pass that so why not combine them. Co-authored-by: Guojin He <guojinhe@meta.com>
smeenai
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Oct 9, 2024
llvm#884) as title. This PR has simliar test case organization as to [PR882](llvm#882) Notice that comparing to OG, this PR combines cases for some pairs of intrinsics such as BI__builtin_neon_vget_lane_f32 and BI__builtin_neon_vdups_lane_f32. They have the same code generated in OG and CIRGen OG separate them into different case handling because it passes mnemonics which are different. CIRGen doesn't pass that so why not combine them. Co-authored-by: Guojin He <guojinhe@meta.com>
smeenai
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Oct 9, 2024
llvm#884) as title. This PR has simliar test case organization as to [PR882](llvm#882) Notice that comparing to OG, this PR combines cases for some pairs of intrinsics such as BI__builtin_neon_vget_lane_f32 and BI__builtin_neon_vdups_lane_f32. They have the same code generated in OG and CIRGen OG separate them into different case handling because it passes mnemonics which are different. CIRGen doesn't pass that so why not combine them. Co-authored-by: Guojin He <guojinhe@meta.com>
keryell
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Oct 19, 2024
llvm#884) as title. This PR has simliar test case organization as to [PR882](llvm#882) Notice that comparing to OG, this PR combines cases for some pairs of intrinsics such as BI__builtin_neon_vget_lane_f32 and BI__builtin_neon_vdups_lane_f32. They have the same code generated in OG and CIRGen OG separate them into different case handling because it passes mnemonics which are different. CIRGen doesn't pass that so why not combine them. Co-authored-by: Guojin He <guojinhe@meta.com>
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as title.
This PR has simliar test case organization as to PR882
Notice that comparing to OG, this PR combines cases for some pairs of intrinsics such as
BI__builtin_neon_vget_lane_f32 and BI__builtin_neon_vdups_lane_f32.
They have the same code generated in OG and CIRGen
OG separate them into different case handling because it passes mnemonics which are different. CIRGen doesn't pass that so why not combine them.