[Profile] Add CFG support for RISC-V #19
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The control transfer instructions are the same for both RV32 and RV64, so we only need one set of regexps. I think this covers all instructions and pseudo-instructions, although I'm not sure if all of them disassembled by objdump.
asb
approved these changes
Sep 30, 2024
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LGTM from a RISC-V perspective in that I believe you've captured all control flow instructions and pseudos (checking against the asm manual pseudos listing in case I forgot any). Matching b* and a line ending with a <label> is the same approach as AArch64, though it seems AArch32 seems to try to more precisely enumerate all the branch names. I think the way you do it is OK, but I'll just mention it as something that gave me pause for thought when reviewing. And if you'd tried to list them all, I'd have had to spend more time trying to double-check you hadn't missed any. So overall the current approach is probably better IMHO.
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Gentle ping for someone on the LNT side |
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The control transfer instructions are the same for both RV32 and RV64, so we only need one set of regexps.
I think this covers all instructions and pseudo-instructions, although I'm not sure if all of them disassembled by objdump.