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[SelectionDAG][RISCV] Support STACK/PATCHPOINT in SoftenFloatOperand. (#165922)
Test float/double/half/bfloat on RISC-V without F extension.
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3 files changed

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-3
lines changed

3 files changed

+127
-3
lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1172,6 +1172,12 @@ bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
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case ISD::FAKE_USE:
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Res = SoftenFloatOp_FAKE_USE(N);
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break;
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case ISD::STACKMAP:
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Res = SoftenFloatOp_STACKMAP(N, OpNo);
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break;
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case ISD::PATCHPOINT:
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Res = SoftenFloatOp_PATCHPOINT(N, OpNo);
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break;
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}
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// If the result is null, the sub-method took care of registering results etc.
@@ -1512,6 +1518,20 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_FAKE_USE(SDNode *N) {
15121518
N->getOperand(0), Op1);
15131519
}
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1521+
SDValue DAGTypeLegalizer::SoftenFloatOp_STACKMAP(SDNode *N, unsigned OpNo) {
1522+
assert(OpNo > 1); // Because the first two arguments are guaranteed legal.
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SmallVector<SDValue> NewOps(N->ops());
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NewOps[OpNo] = GetSoftenedFloat(NewOps[OpNo]);
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return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
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}
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SDValue DAGTypeLegalizer::SoftenFloatOp_PATCHPOINT(SDNode *N, unsigned OpNo) {
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assert(OpNo >= 7);
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SmallVector<SDValue> NewOps(N->ops());
1531+
NewOps[OpNo] = GetSoftenedFloat(NewOps[OpNo]);
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return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
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}
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15151535
//===----------------------------------------------------------------------===//
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// Float Result Expansion
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//===----------------------------------------------------------------------===//

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -658,6 +658,8 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
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SDValue SoftenFloatOp_ATOMIC_STORE(SDNode *N, unsigned OpNo);
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SDValue SoftenFloatOp_FCOPYSIGN(SDNode *N);
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SDValue SoftenFloatOp_FAKE_USE(SDNode *N);
661+
SDValue SoftenFloatOp_STACKMAP(SDNode *N, unsigned OpNo);
662+
SDValue SoftenFloatOp_PATCHPOINT(SDNode *N, unsigned OpNo);
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662664
//===--------------------------------------------------------------------===//
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// Float Expansion Support: LegalizeFloatTypes.cpp

‎llvm/test/CodeGen/RISCV/rv64-stackmap.ll‎

Lines changed: 105 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,11 +7,11 @@
77
; CHECK-NEXT: .byte 0
88
; CHECK-NEXT: .half 0
99
; Num Functions
10-
; CHECK-NEXT: .word 12
10+
; CHECK-NEXT: .word 13
1111
; Num LargeConstants
12-
; CHECK-NEXT: .word 2
12+
; CHECK-NEXT: .word 3
1313
; Num Callsites
14-
; CHECK-NEXT: .word 16
14+
; CHECK-NEXT: .word 17
1515

1616
; Functions and stack size
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; CHECK-NEXT: .quad constantargs
@@ -50,10 +50,14 @@
5050
; CHECK-NEXT: .quad needsStackRealignment
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; CHECK-NEXT: .quad -1
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad floats
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; CHECK-NEXT: .quad 32
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; CHECK-NEXT: .quad 1
5356

5457
; Num LargeConstants
5558
; CHECK-NEXT: .quad 4294967295
5659
; CHECK-NEXT: .quad 4294967296
60+
; CHECK-NEXT: .quad 4609434218613702656
5761

5862
; Constant arguments
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;
@@ -379,6 +383,104 @@ define void @needsStackRealignment() {
379383
}
380384
declare void @escape_values(...)
381385

386+
; CHECK-LABEL: .word .L{{.*}}-floats
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; CHECK-NEXT: .half 0
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; Num Locations
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; CHECK-NEXT: .half 12
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; Loc 0: constant float as constant integer
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .half 8
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; CHECK-NEXT: .half 0
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; CHECK-NEXT: .half 0
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; CHECK-NEXT: .word
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; Loc 1: constant double as large constant integer
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; CHECK-NEXT: .byte 5
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .half 8
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; CHECK-NEXT: .half 0
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; CHECK-NEXT: .half 0
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; CHECK-NEXT: .word
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; Loc 2: constant half as constant integer
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .half 8
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; CHECK-NEXT: .half 0
409+
; CHECK-NEXT: .half 0
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; CHECK-NEXT: .word
411+
; Loc 3: constant bfloat as constant integer
412+
; CHECK-NEXT: .byte 4
413+
; CHECK-NEXT: .byte 0
414+
; CHECK-NEXT: .half 8
415+
; CHECK-NEXT: .half 0
416+
; CHECK-NEXT: .half 0
417+
; CHECK-NEXT: .word
418+
; Loc 4: float value in X register
419+
; CHECK-NEXT: .byte 1
420+
; CHECK-NEXT: .byte 0
421+
; CHECK-NEXT: .half 8
422+
; CHECK-NEXT: .half 10
423+
; CHECK-NEXT: .half 0
424+
; CHECK-NEXT: .word
425+
; Loc 5: double value in X register
426+
; CHECK-NEXT: .byte 1
427+
; CHECK-NEXT: .byte 0
428+
; CHECK-NEXT: .half 8
429+
; CHECK-NEXT: .half 11
430+
; CHECK-NEXT: .half 0
431+
; CHECK-NEXT: .word
432+
; Loc 6: half value in X register
433+
; CHECK-NEXT: .byte 1
434+
; CHECK-NEXT: .byte 0
435+
; CHECK-NEXT: .half 8
436+
; CHECK-NEXT: .half 12
437+
; CHECK-NEXT: .half 0
438+
; CHECK-NEXT: .word
439+
; Loc 7: bfloat value in X register
440+
; CHECK-NEXT: .byte 1
441+
; CHECK-NEXT: .byte 0
442+
; CHECK-NEXT: .half 8
443+
; CHECK-NEXT: .half 13
444+
; CHECK-NEXT: .half 0
445+
; CHECK-NEXT: .word
446+
; Loc 8: float on stack
447+
; CHECK-NEXT: .byte 2
448+
; CHECK-NEXT: .byte 0
449+
; CHECK-NEXT: .half 8
450+
; CHECK-NEXT: .half 2
451+
; CHECK-NEXT: .half 0
452+
; CHECK-NEXT: .word
453+
; Loc 9: double on stack
454+
; CHECK-NEXT: .byte 2
455+
; CHECK-NEXT: .byte 0
456+
; CHECK-NEXT: .half 8
457+
; CHECK-NEXT: .half 2
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; CHECK-NEXT: .half 0
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; CHECK-NEXT: .word
460+
; Loc 10: half on stack
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; CHECK-NEXT: .byte 2
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; CHECK-NEXT: .byte 0
463+
; CHECK-NEXT: .half 8
464+
; CHECK-NEXT: .half 2
465+
; CHECK-NEXT: .half 0
466+
; CHECK-NEXT: .word
467+
; Loc 11: bfloat on stack
468+
; CHECK-NEXT: .byte 2
469+
; CHECK-NEXT: .byte 0
470+
; CHECK-NEXT: .half 8
471+
; CHECK-NEXT: .half 2
472+
; CHECK-NEXT: .half 0
473+
; CHECK-NEXT: .word
474+
define void @floats(float %f, double %g, half %h, bfloat %i) {
475+
%ff = alloca float
476+
%gg = alloca double
477+
%hh = alloca half
478+
%ii = alloca bfloat
479+
call void (i64, i32, ...) @llvm.experimental.stackmap(i64 888, i32 0, float 1.25,
480+
double 1.5, half 1.5, bfloat 1.5, float %f, double %g, half %h, bfloat %i, ptr %ff, ptr %gg, ptr %hh, ptr %ii)
481+
ret void
482+
}
483+
382484
declare void @llvm.experimental.stackmap(i64, i32, ...)
383485
declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
384486
declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)

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