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[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)
This maybe a bug which is introduced by commit 6749ae3, and has been present ever since. In this case, `OtherReg` always overlaps with `DstReg` cause they from the `Copy` all.
1 parent 0ef522f commit 0859ac5

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55 files changed

+5938
-6055
lines changed

‎llvm/lib/CodeGen/RegisterCoalescer.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4150,7 +4150,7 @@ bool RegisterCoalescer::applyTerminalRule(const MachineInstr &Copy) const {
41504150
continue;
41514151
Register OtherSrcReg, OtherReg;
41524152
unsigned OtherSrcSubReg = 0, OtherSubReg = 0;
4153-
if (!isMoveInstr(*TRI, &Copy, OtherSrcReg, OtherReg, OtherSrcSubReg,
4153+
if (!isMoveInstr(*TRI, &MI, OtherSrcReg, OtherReg, OtherSrcSubReg,
41544154
OtherSubReg))
41554155
return false;
41564156
if (OtherReg == SrcReg)

‎llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -803,20 +803,20 @@ define i64 @red_mla_dup_ext_u8_s8_s64(ptr noalias noundef readonly captures(none
803803
; CHECK-SD-NEXT: smlal2 v4.2d, v16.4s, v20.4s
804804
; CHECK-SD-NEXT: smlal v6.2d, v16.2s, v20.2s
805805
; CHECK-SD-NEXT: smlal v3.2d, v16.2s, v19.2s
806-
; CHECK-SD-NEXT: smlal2 v1.2d, v16.4s, v18.4s
806+
; CHECK-SD-NEXT: smlal2 v0.2d, v16.4s, v18.4s
807807
; CHECK-SD-NEXT: smlal v7.2d, v16.2s, v17.2s
808-
; CHECK-SD-NEXT: smlal v0.2d, v16.2s, v18.2s
808+
; CHECK-SD-NEXT: smlal v1.2d, v16.2s, v18.2s
809809
; CHECK-SD-NEXT: smlal2 v5.2d, v16.4s, v17.4s
810810
; CHECK-SD-NEXT: b.ne .LBB6_7
811811
; CHECK-SD-NEXT: // %bb.8: // %middle.block
812-
; CHECK-SD-NEXT: add v0.2d, v0.2d, v6.2d
812+
; CHECK-SD-NEXT: add v1.2d, v1.2d, v6.2d
813813
; CHECK-SD-NEXT: add v3.2d, v3.2d, v7.2d
814814
; CHECK-SD-NEXT: cmp x10, x9
815-
; CHECK-SD-NEXT: add v1.2d, v1.2d, v4.2d
815+
; CHECK-SD-NEXT: add v0.2d, v0.2d, v4.2d
816816
; CHECK-SD-NEXT: add v2.2d, v2.2d, v5.2d
817-
; CHECK-SD-NEXT: add v0.2d, v0.2d, v3.2d
818-
; CHECK-SD-NEXT: add v1.2d, v1.2d, v2.2d
819-
; CHECK-SD-NEXT: add v0.2d, v0.2d, v1.2d
817+
; CHECK-SD-NEXT: add v1.2d, v1.2d, v3.2d
818+
; CHECK-SD-NEXT: add v0.2d, v0.2d, v2.2d
819+
; CHECK-SD-NEXT: add v0.2d, v1.2d, v0.2d
820820
; CHECK-SD-NEXT: addp d0, v0.2d
821821
; CHECK-SD-NEXT: fmov x8, d0
822822
; CHECK-SD-NEXT: b.eq .LBB6_15

‎llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -35,15 +35,15 @@ define i32 @check_deinterleaving_has_deinterleave(ptr %a) {
3535
; CHECK-LABEL: check_deinterleaving_has_deinterleave:
3636
; CHECK: // %bb.0: // %entry
3737
; CHECK-NEXT: movi v0.2d, #0000000000000000
38-
; CHECK-NEXT: movi v1.4s, #1
38+
; CHECK-NEXT: movi v2.4s, #1
3939
; CHECK-NEXT: add x8, x0, #16
40-
; CHECK-NEXT: movi v3.2d, #0000000000000000
41-
; CHECK-NEXT: movi v2.2d, #0000000000000000
42-
; CHECK-NEXT: mov w9, #32 // =0x20
40+
; CHECK-NEXT: movi v1.2d, #0000000000000000
4341
; CHECK-NEXT: movi v4.2d, #0000000000000000
42+
; CHECK-NEXT: mov w9, #32 // =0x20
43+
; CHECK-NEXT: movi v3.2d, #0000000000000000
4444
; CHECK-NEXT: movi v5.2d, #0000000000000000
45-
; CHECK-NEXT: movi v7.2d, #0000000000000000
4645
; CHECK-NEXT: movi v6.2d, #0000000000000000
46+
; CHECK-NEXT: movi v7.2d, #0000000000000000
4747
; CHECK-NEXT: movi v16.2d, #0000000000000000
4848
; CHECK-NEXT: .LBB1_1: // %vector.body
4949
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
@@ -64,31 +64,31 @@ define i32 @check_deinterleaving_has_deinterleave(ptr %a) {
6464
; CHECK-NEXT: ushll v24.4s, v18.4h, #0
6565
; CHECK-NEXT: ushll2 v18.4s, v18.8h, #0
6666
; CHECK-NEXT: ushll v20.4s, v20.4h, #0
67-
; CHECK-NEXT: and v21.16b, v21.16b, v1.16b
68-
; CHECK-NEXT: and v19.16b, v19.16b, v1.16b
69-
; CHECK-NEXT: and v22.16b, v22.16b, v1.16b
70-
; CHECK-NEXT: and v17.16b, v17.16b, v1.16b
71-
; CHECK-NEXT: and v23.16b, v23.16b, v1.16b
72-
; CHECK-NEXT: and v24.16b, v24.16b, v1.16b
73-
; CHECK-NEXT: and v18.16b, v18.16b, v1.16b
74-
; CHECK-NEXT: and v20.16b, v20.16b, v1.16b
75-
; CHECK-NEXT: add v4.4s, v4.4s, v19.4s
76-
; CHECK-NEXT: add v2.4s, v2.4s, v21.4s
77-
; CHECK-NEXT: add v0.4s, v0.4s, v22.4s
78-
; CHECK-NEXT: add v3.4s, v3.4s, v17.4s
67+
; CHECK-NEXT: and v21.16b, v21.16b, v2.16b
68+
; CHECK-NEXT: and v19.16b, v19.16b, v2.16b
69+
; CHECK-NEXT: and v22.16b, v22.16b, v2.16b
70+
; CHECK-NEXT: and v17.16b, v17.16b, v2.16b
71+
; CHECK-NEXT: and v23.16b, v23.16b, v2.16b
72+
; CHECK-NEXT: and v24.16b, v24.16b, v2.16b
73+
; CHECK-NEXT: and v18.16b, v18.16b, v2.16b
74+
; CHECK-NEXT: and v20.16b, v20.16b, v2.16b
75+
; CHECK-NEXT: add v5.4s, v5.4s, v19.4s
76+
; CHECK-NEXT: add v3.4s, v3.4s, v21.4s
77+
; CHECK-NEXT: add v1.4s, v1.4s, v22.4s
78+
; CHECK-NEXT: add v4.4s, v4.4s, v17.4s
7979
; CHECK-NEXT: add v16.4s, v16.4s, v23.4s
80-
; CHECK-NEXT: add v5.4s, v5.4s, v24.4s
81-
; CHECK-NEXT: add v6.4s, v6.4s, v20.4s
82-
; CHECK-NEXT: add v7.4s, v7.4s, v18.4s
80+
; CHECK-NEXT: add v6.4s, v6.4s, v24.4s
81+
; CHECK-NEXT: add v7.4s, v7.4s, v20.4s
82+
; CHECK-NEXT: add v0.4s, v0.4s, v18.4s
8383
; CHECK-NEXT: b.ne .LBB1_1
8484
; CHECK-NEXT: // %bb.2: // %middle.block
85-
; CHECK-NEXT: add v1.4s, v7.4s, v3.4s
86-
; CHECK-NEXT: add v3.4s, v16.4s, v4.4s
87-
; CHECK-NEXT: add v0.4s, v5.4s, v0.4s
88-
; CHECK-NEXT: add v2.4s, v6.4s, v2.4s
89-
; CHECK-NEXT: add v1.4s, v1.4s, v3.4s
85+
; CHECK-NEXT: add v0.4s, v0.4s, v4.4s
86+
; CHECK-NEXT: add v2.4s, v16.4s, v5.4s
87+
; CHECK-NEXT: add v1.4s, v6.4s, v1.4s
88+
; CHECK-NEXT: add v3.4s, v7.4s, v3.4s
9089
; CHECK-NEXT: add v0.4s, v0.4s, v2.4s
91-
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
90+
; CHECK-NEXT: add v1.4s, v1.4s, v3.4s
91+
; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
9292
; CHECK-NEXT: addv s0, v0.4s
9393
; CHECK-NEXT: fmov w0, s0
9494
; CHECK-NEXT: ret

‎llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -31,14 +31,14 @@ define %"class.std::complex" @complex_mul_v2f64(ptr %a, ptr %b) {
3131
; CHECK-NEXT: ldr z5, [x1]
3232
; CHECK-NEXT: add x1, x1, x10
3333
; CHECK-NEXT: add x0, x0, x10
34-
; CHECK-NEXT: fcmla z0.d, p0/m, z5.d, z3.d, #0
35-
; CHECK-NEXT: fcmla z1.d, p0/m, z4.d, z2.d, #0
36-
; CHECK-NEXT: fcmla z0.d, p0/m, z5.d, z3.d, #90
37-
; CHECK-NEXT: fcmla z1.d, p0/m, z4.d, z2.d, #90
34+
; CHECK-NEXT: fcmla z1.d, p0/m, z5.d, z3.d, #0
35+
; CHECK-NEXT: fcmla z0.d, p0/m, z4.d, z2.d, #0
36+
; CHECK-NEXT: fcmla z1.d, p0/m, z5.d, z3.d, #90
37+
; CHECK-NEXT: fcmla z0.d, p0/m, z4.d, z2.d, #90
3838
; CHECK-NEXT: b.ne .LBB0_1
3939
; CHECK-NEXT: // %bb.2: // %exit.block
40-
; CHECK-NEXT: uzp1 z2.d, z0.d, z1.d
41-
; CHECK-NEXT: uzp2 z1.d, z0.d, z1.d
40+
; CHECK-NEXT: uzp1 z2.d, z1.d, z0.d
41+
; CHECK-NEXT: uzp2 z1.d, z1.d, z0.d
4242
; CHECK-NEXT: faddv d0, p0, z2.d
4343
; CHECK-NEXT: faddv d1, p0, z1.d
4444
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
@@ -205,20 +205,20 @@ define %"class.std::complex" @complex_mul_v2f64_unrolled(ptr %a, ptr %b) {
205205
; CHECK-NEXT: ldr z18, [x1, #3, mul vl]
206206
; CHECK-NEXT: ldr z19, [x1, #2, mul vl]
207207
; CHECK-NEXT: add x1, x1, x10
208-
; CHECK-NEXT: fcmla z0.d, p0/m, z16.d, z5.d, #0
209-
; CHECK-NEXT: fcmla z1.d, p0/m, z7.d, z4.d, #0
208+
; CHECK-NEXT: fcmla z1.d, p0/m, z16.d, z5.d, #0
209+
; CHECK-NEXT: fcmla z0.d, p0/m, z7.d, z4.d, #0
210210
; CHECK-NEXT: fcmla z3.d, p0/m, z18.d, z6.d, #0
211211
; CHECK-NEXT: fcmla z2.d, p0/m, z19.d, z17.d, #0
212-
; CHECK-NEXT: fcmla z0.d, p0/m, z16.d, z5.d, #90
213-
; CHECK-NEXT: fcmla z1.d, p0/m, z7.d, z4.d, #90
212+
; CHECK-NEXT: fcmla z1.d, p0/m, z16.d, z5.d, #90
213+
; CHECK-NEXT: fcmla z0.d, p0/m, z7.d, z4.d, #90
214214
; CHECK-NEXT: fcmla z3.d, p0/m, z18.d, z6.d, #90
215215
; CHECK-NEXT: fcmla z2.d, p0/m, z19.d, z17.d, #90
216216
; CHECK-NEXT: b.ne .LBB2_1
217217
; CHECK-NEXT: // %bb.2: // %exit.block
218218
; CHECK-NEXT: uzp1 z4.d, z2.d, z3.d
219-
; CHECK-NEXT: uzp1 z5.d, z0.d, z1.d
219+
; CHECK-NEXT: uzp1 z5.d, z1.d, z0.d
220220
; CHECK-NEXT: uzp2 z2.d, z2.d, z3.d
221-
; CHECK-NEXT: uzp2 z0.d, z0.d, z1.d
221+
; CHECK-NEXT: uzp2 z0.d, z1.d, z0.d
222222
; CHECK-NEXT: fadd z1.d, z4.d, z5.d
223223
; CHECK-NEXT: fadd z2.d, z2.d, z0.d
224224
; CHECK-NEXT: faddv d0, p0, z1.d

‎llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -25,14 +25,14 @@ define dso_local %"struct.std::complex" @complex_mul_v2f64(ptr %a, ptr %b) {
2525
; CHECK-NEXT: ldp q3, q2, [x9]
2626
; CHECK-NEXT: cmp x8, #1600
2727
; CHECK-NEXT: ldp q5, q4, [x10]
28-
; CHECK-NEXT: fcmla v0.2d, v5.2d, v3.2d, #0
29-
; CHECK-NEXT: fcmla v1.2d, v4.2d, v2.2d, #0
30-
; CHECK-NEXT: fcmla v0.2d, v5.2d, v3.2d, #90
31-
; CHECK-NEXT: fcmla v1.2d, v4.2d, v2.2d, #90
28+
; CHECK-NEXT: fcmla v1.2d, v5.2d, v3.2d, #0
29+
; CHECK-NEXT: fcmla v0.2d, v4.2d, v2.2d, #0
30+
; CHECK-NEXT: fcmla v1.2d, v5.2d, v3.2d, #90
31+
; CHECK-NEXT: fcmla v0.2d, v4.2d, v2.2d, #90
3232
; CHECK-NEXT: b.ne .LBB0_1
3333
; CHECK-NEXT: // %bb.2: // %middle.block
34-
; CHECK-NEXT: zip2 v2.2d, v0.2d, v1.2d
35-
; CHECK-NEXT: zip1 v0.2d, v0.2d, v1.2d
34+
; CHECK-NEXT: zip2 v2.2d, v1.2d, v0.2d
35+
; CHECK-NEXT: zip1 v0.2d, v1.2d, v0.2d
3636
; CHECK-NEXT: faddp d0, v0.2d
3737
; CHECK-NEXT: faddp d1, v2.2d
3838
; CHECK-NEXT: ret
@@ -159,20 +159,20 @@ define %"struct.std::complex" @complex_mul_v2f64_unrolled(ptr %a, ptr %b) {
159159
; CHECK-NEXT: ldp q17, q16, [x8], #64
160160
; CHECK-NEXT: ldp q19, q18, [x9], #64
161161
; CHECK-NEXT: fcmla v2.2d, v7.2d, v5.2d, #0
162-
; CHECK-NEXT: fcmla v0.2d, v6.2d, v4.2d, #0
163-
; CHECK-NEXT: fcmla v1.2d, v19.2d, v17.2d, #0
162+
; CHECK-NEXT: fcmla v1.2d, v6.2d, v4.2d, #0
163+
; CHECK-NEXT: fcmla v0.2d, v19.2d, v17.2d, #0
164164
; CHECK-NEXT: fcmla v3.2d, v18.2d, v16.2d, #0
165165
; CHECK-NEXT: fcmla v2.2d, v7.2d, v5.2d, #90
166-
; CHECK-NEXT: fcmla v0.2d, v6.2d, v4.2d, #90
167-
; CHECK-NEXT: fcmla v1.2d, v19.2d, v17.2d, #90
166+
; CHECK-NEXT: fcmla v1.2d, v6.2d, v4.2d, #90
167+
; CHECK-NEXT: fcmla v0.2d, v19.2d, v17.2d, #90
168168
; CHECK-NEXT: fcmla v3.2d, v18.2d, v16.2d, #90
169169
; CHECK-NEXT: b.ne .LBB2_1
170170
; CHECK-NEXT: // %bb.2: // %middle.block
171-
; CHECK-NEXT: zip2 v4.2d, v1.2d, v3.2d
172-
; CHECK-NEXT: zip1 v1.2d, v1.2d, v3.2d
173-
; CHECK-NEXT: zip2 v3.2d, v2.2d, v0.2d
174-
; CHECK-NEXT: zip1 v0.2d, v2.2d, v0.2d
175-
; CHECK-NEXT: fadd v0.2d, v1.2d, v0.2d
171+
; CHECK-NEXT: zip2 v4.2d, v0.2d, v3.2d
172+
; CHECK-NEXT: zip1 v0.2d, v0.2d, v3.2d
173+
; CHECK-NEXT: zip2 v3.2d, v2.2d, v1.2d
174+
; CHECK-NEXT: zip1 v1.2d, v2.2d, v1.2d
175+
; CHECK-NEXT: fadd v0.2d, v0.2d, v1.2d
176176
; CHECK-NEXT: fadd v1.2d, v4.2d, v3.2d
177177
; CHECK-NEXT: faddp d0, v0.2d
178178
; CHECK-NEXT: faddp d1, v1.2d

‎llvm/test/CodeGen/AArch64/machine-sink-kill-flags.ll‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,9 @@ define i32 @test(ptr %ptr) {
1616
; CHECK-NEXT: mov w9, wzr
1717
; CHECK-NEXT: LBB0_1: ; %.thread
1818
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
19+
; CHECK-NEXT: lsr w11, w9, #1
1920
; CHECK-NEXT: sub w10, w9, #1
20-
; CHECK-NEXT: lsr w9, w9, #1
21+
; CHECK-NEXT: mov w9, w11
2122
; CHECK-NEXT: tbnz w10, #0, LBB0_1
2223
; CHECK-NEXT: ; %bb.2: ; %bb343
2324
; CHECK-NEXT: and w9, w10, #0x1

‎llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -147,15 +147,15 @@ define <2 x float> @extract_v2f32_nxv16f32_2(<vscale x 16 x float> %arg) {
147147
define <4 x i1> @extract_v4i1_nxv32i1_0(<vscale x 32 x i1> %arg) {
148148
; CHECK-LABEL: extract_v4i1_nxv32i1_0:
149149
; CHECK: // %bb.0:
150-
; CHECK-NEXT: mov z0.b, p0/z, #1 // =0x1
151-
; CHECK-NEXT: umov w8, v0.b[1]
152-
; CHECK-NEXT: mov v1.16b, v0.16b
150+
; CHECK-NEXT: mov z1.b, p0/z, #1 // =0x1
151+
; CHECK-NEXT: umov w8, v1.b[1]
152+
; CHECK-NEXT: mov v0.16b, v1.16b
153+
; CHECK-NEXT: umov w9, v1.b[2]
153154
; CHECK-NEXT: mov v0.h[1], w8
154-
; CHECK-NEXT: umov w8, v1.b[2]
155-
; CHECK-NEXT: mov v0.h[2], w8
156155
; CHECK-NEXT: umov w8, v1.b[3]
156+
; CHECK-NEXT: mov v0.h[2], w9
157157
; CHECK-NEXT: mov v0.h[3], w8
158-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
158+
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
159159
; CHECK-NEXT: ret
160160
%ext = call <4 x i1> @llvm.vector.extract.v4i1.nxv32i1(<vscale x 32 x i1> %arg, i64 0)
161161
ret <4 x i1> %ext

‎llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -248,15 +248,15 @@ define <2 x i1> @extract_v2i1_nxv2i1(<vscale x 2 x i1> %inmask) {
248248
define <4 x i1> @extract_v4i1_nxv4i1(<vscale x 4 x i1> %inmask) {
249249
; CHECK-LABEL: extract_v4i1_nxv4i1:
250250
; CHECK: // %bb.0:
251-
; CHECK-NEXT: mov z0.s, p0/z, #1 // =0x1
252-
; CHECK-NEXT: mov w8, v0.s[1]
253-
; CHECK-NEXT: mov v1.16b, v0.16b
251+
; CHECK-NEXT: mov z1.s, p0/z, #1 // =0x1
252+
; CHECK-NEXT: mov w8, v1.s[1]
253+
; CHECK-NEXT: mov v0.16b, v1.16b
254+
; CHECK-NEXT: mov w9, v1.s[2]
254255
; CHECK-NEXT: mov v0.h[1], w8
255-
; CHECK-NEXT: mov w8, v1.s[2]
256-
; CHECK-NEXT: mov v0.h[2], w8
257256
; CHECK-NEXT: mov w8, v1.s[3]
257+
; CHECK-NEXT: mov v0.h[2], w9
258258
; CHECK-NEXT: mov v0.h[3], w8
259-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
259+
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
260260
; CHECK-NEXT: ret
261261
%mask = call <4 x i1> @llvm.vector.extract.v4i1.nxv4i1(<vscale x 4 x i1> %inmask, i64 0)
262262
ret <4 x i1> %mask
@@ -265,23 +265,23 @@ define <4 x i1> @extract_v4i1_nxv4i1(<vscale x 4 x i1> %inmask) {
265265
define <8 x i1> @extract_v8i1_nxv8i1(<vscale x 8 x i1> %inmask) {
266266
; CHECK-LABEL: extract_v8i1_nxv8i1:
267267
; CHECK: // %bb.0:
268-
; CHECK-NEXT: mov z0.h, p0/z, #1 // =0x1
269-
; CHECK-NEXT: umov w8, v0.h[1]
270-
; CHECK-NEXT: mov v1.16b, v0.16b
268+
; CHECK-NEXT: mov z1.h, p0/z, #1 // =0x1
269+
; CHECK-NEXT: umov w8, v1.h[1]
270+
; CHECK-NEXT: mov v0.16b, v1.16b
271+
; CHECK-NEXT: umov w9, v1.h[2]
271272
; CHECK-NEXT: mov v0.b[1], w8
272-
; CHECK-NEXT: umov w8, v1.h[2]
273-
; CHECK-NEXT: mov v0.b[2], w8
274273
; CHECK-NEXT: umov w8, v1.h[3]
274+
; CHECK-NEXT: mov v0.b[2], w9
275+
; CHECK-NEXT: umov w9, v1.h[4]
275276
; CHECK-NEXT: mov v0.b[3], w8
276-
; CHECK-NEXT: umov w8, v1.h[4]
277-
; CHECK-NEXT: mov v0.b[4], w8
278277
; CHECK-NEXT: umov w8, v1.h[5]
278+
; CHECK-NEXT: mov v0.b[4], w9
279+
; CHECK-NEXT: umov w9, v1.h[6]
279280
; CHECK-NEXT: mov v0.b[5], w8
280-
; CHECK-NEXT: umov w8, v1.h[6]
281-
; CHECK-NEXT: mov v0.b[6], w8
282281
; CHECK-NEXT: umov w8, v1.h[7]
282+
; CHECK-NEXT: mov v0.b[6], w9
283283
; CHECK-NEXT: mov v0.b[7], w8
284-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
284+
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
285285
; CHECK-NEXT: ret
286286
%mask = call <8 x i1> @llvm.vector.extract.v8i1.nxv8i1(<vscale x 8 x i1> %inmask, i64 0)
287287
ret <8 x i1> %mask

‎llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,15 +8,15 @@ target triple = "aarch64-unknown-linux-gnu"
88
define <4 x i1> @reshuffle_v4i1_nxv4i1(<vscale x 4 x i1> %a) #0 {
99
; CHECK-LABEL: reshuffle_v4i1_nxv4i1:
1010
; CHECK: // %bb.0:
11-
; CHECK-NEXT: mov z0.s, p0/z, #1 // =0x1
12-
; CHECK-NEXT: mov w8, v0.s[1]
13-
; CHECK-NEXT: mov v1.16b, v0.16b
11+
; CHECK-NEXT: mov z1.s, p0/z, #1 // =0x1
12+
; CHECK-NEXT: mov w8, v1.s[1]
13+
; CHECK-NEXT: mov v0.16b, v1.16b
14+
; CHECK-NEXT: mov w9, v1.s[2]
1415
; CHECK-NEXT: mov v0.h[1], w8
15-
; CHECK-NEXT: mov w8, v1.s[2]
16-
; CHECK-NEXT: mov v0.h[2], w8
1716
; CHECK-NEXT: mov w8, v1.s[3]
17+
; CHECK-NEXT: mov v0.h[2], w9
1818
; CHECK-NEXT: mov v0.h[3], w8
19-
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
19+
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
2020
; CHECK-NEXT: ret
2121
%el0 = extractelement <vscale x 4 x i1> %a, i32 0
2222
%el1 = extractelement <vscale x 4 x i1> %a, i32 1

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