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[LoongArch][NFC] Pre-commit tests for vector fptrunc from vxf64 to vxf32
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‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptrunc.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK
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;; fptrunc
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define void @fptrunc_v4f64_to_v4f32(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: fptrunc_v4f64_to_v4f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvpickve.d $xr1, $xr0, 1
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; CHECK-NEXT: fcvt.s.d $fa1, $fa1
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; CHECK-NEXT: xvpickve.d $xr2, $xr0, 0
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; CHECK-NEXT: fcvt.s.d $fa2, $fa2
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; CHECK-NEXT: vextrins.w $vr2, $vr1, 16
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; CHECK-NEXT: xvpickve.d $xr1, $xr0, 2
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; CHECK-NEXT: fcvt.s.d $fa1, $fa1
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; CHECK-NEXT: vextrins.w $vr2, $vr1, 32
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; CHECK-NEXT: xvpickve.d $xr0, $xr0, 3
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; CHECK-NEXT: fcvt.s.d $fa0, $fa0
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; CHECK-NEXT: vextrins.w $vr2, $vr0, 48
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; CHECK-NEXT: vst $vr2, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x double>, ptr %a0
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%trunc = fptrunc <4 x double> %v0 to <4 x float>
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store <4 x float> %trunc, ptr %res
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ret void
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}
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define void @fptrunc_v8f64_to_v8f32(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: fptrunc_v8f64_to_v8f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 32
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; CHECK-NEXT: xvld $xr1, $a1, 0
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; CHECK-NEXT: xvpickve.d $xr2, $xr0, 1
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; CHECK-NEXT: fcvt.s.d $fa2, $fa2
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; CHECK-NEXT: xvpickve.d $xr3, $xr0, 0
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; CHECK-NEXT: fcvt.s.d $fa3, $fa3
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; CHECK-NEXT: vextrins.w $vr3, $vr2, 16
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; CHECK-NEXT: xvpickve.d $xr2, $xr0, 2
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; CHECK-NEXT: fcvt.s.d $fa2, $fa2
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; CHECK-NEXT: vextrins.w $vr3, $vr2, 32
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; CHECK-NEXT: xvpickve.d $xr0, $xr0, 3
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; CHECK-NEXT: fcvt.s.d $fa0, $fa0
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; CHECK-NEXT: vextrins.w $vr3, $vr0, 48
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; CHECK-NEXT: xvpickve.d $xr0, $xr1, 1
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; CHECK-NEXT: fcvt.s.d $fa0, $fa0
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; CHECK-NEXT: xvpickve.d $xr2, $xr1, 0
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; CHECK-NEXT: fcvt.s.d $fa2, $fa2
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; CHECK-NEXT: vextrins.w $vr2, $vr0, 16
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; CHECK-NEXT: xvpickve.d $xr0, $xr1, 2
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; CHECK-NEXT: fcvt.s.d $fa0, $fa0
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; CHECK-NEXT: vextrins.w $vr2, $vr0, 32
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; CHECK-NEXT: xvpickve.d $xr0, $xr1, 3
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; CHECK-NEXT: fcvt.s.d $fa0, $fa0
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; CHECK-NEXT: vextrins.w $vr2, $vr0, 48
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; CHECK-NEXT: xvpermi.q $xr2, $xr3, 2
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; CHECK-NEXT: xvst $xr2, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x double>, ptr %a0
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%trunc = fptrunc <8 x double> %v0 to <8 x float>
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store <8 x float> %trunc, ptr %res
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ret void
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}

‎llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptrunc.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
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;; fptrunc
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define void @fptrunc_v1f64_to_v1f32(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: fptrunc_v1f64_to_v1f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fld.d $fa0, $a1, 0
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; CHECK-NEXT: fcvt.s.d $fa0, $fa0
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; CHECK-NEXT: fst.s $fa0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <1 x double>, ptr %a0
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%trunc = fptrunc <1 x double> %v0 to <1 x float>
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store <1 x float> %trunc, ptr %res
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ret void
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}
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define void @fptrunc_v2f64_to_v2f32(ptr %res, ptr %a0) nounwind {
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; LA32-LABEL: fptrunc_v2f64_to_v2f32:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: vld $vr0, $a1, 0
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; LA32-NEXT: vreplvei.d $vr1, $vr0, 0
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; LA32-NEXT: fcvt.s.d $fa1, $fa1
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; LA32-NEXT: vreplvei.d $vr0, $vr0, 1
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; LA32-NEXT: fcvt.s.d $fa0, $fa0
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; LA32-NEXT: fst.s $fa0, $a0, 4
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; LA32-NEXT: fst.s $fa1, $a0, 0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: fptrunc_v2f64_to_v2f32:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: vld $vr0, $a1, 0
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; LA64-NEXT: vreplvei.d $vr1, $vr0, 1
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; LA64-NEXT: fcvt.s.d $fa1, $fa1
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; LA64-NEXT: vreplvei.d $vr0, $vr0, 0
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; LA64-NEXT: fcvt.s.d $fa0, $fa0
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; LA64-NEXT: vextrins.w $vr0, $vr1, 16
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; LA64-NEXT: vstelm.d $vr0, $a0, 0, 0
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; LA64-NEXT: ret
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entry:
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%v0 = load <2 x double>, ptr %a0
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%trunc = fptrunc <2 x double> %v0 to <2 x float>
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store <2 x float> %trunc, ptr %res
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ret void
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}
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define void @fptrunc_v4f64_to_v4f32(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: fptrunc_v4f64_to_v4f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a1, 16
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; CHECK-NEXT: vreplvei.d $vr2, $vr0, 1
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; CHECK-NEXT: fcvt.s.d $fa2, $fa2
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; CHECK-NEXT: vreplvei.d $vr0, $vr0, 0
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; CHECK-NEXT: fcvt.s.d $fa0, $fa0
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; CHECK-NEXT: vextrins.w $vr0, $vr2, 16
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; CHECK-NEXT: vreplvei.d $vr2, $vr1, 0
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; CHECK-NEXT: fcvt.s.d $fa2, $fa2
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; CHECK-NEXT: vextrins.w $vr0, $vr2, 32
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; CHECK-NEXT: vreplvei.d $vr1, $vr1, 1
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; CHECK-NEXT: fcvt.s.d $fa1, $fa1
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; CHECK-NEXT: vextrins.w $vr0, $vr1, 48
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x double>, ptr %a0
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%trunc = fptrunc <4 x double> %v0 to <4 x float>
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store <4 x float> %trunc, ptr %res
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ret void
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}

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