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[InstCombine] Accumulate the limit only on the instructions that require
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1 parent 0fd9da5 commit 0fb1679

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8 files changed

+85
-54
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8 files changed

+85
-54
lines changed

‎llvm/lib/Analysis/Loads.cpp‎

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -539,6 +539,16 @@ static bool areNonOverlapSameBaseLoadAndStore(const Value *LoadPtr,
539539
return LoadRange.intersectWith(StoreRange).isEmptySet();
540540
}
541541

542+
static bool maybeAvailableLoadStore(Instruction *Inst) {
543+
switch (Inst->getOpcode()) {
544+
case Instruction::Load:
545+
case Instruction::Store:
546+
return true;
547+
default:
548+
return isa<MemSetInst>(Inst);
549+
}
550+
}
551+
542552
static Value *getAvailableLoadStore(Instruction *Inst, const Value *Ptr,
543553
Type *AccessTy, bool AtLeastAtomic,
544554
const DataLayout &DL, bool *IsLoadCSE) {
@@ -653,7 +663,7 @@ Value *llvm::findAvailablePtrLoadStore(
653663
++(*NumScanedInst);
654664

655665
// Don't scan huge blocks.
656-
if (MaxInstsToScan-- == 0)
666+
if (maybeAvailableLoadStore(Inst) && MaxInstsToScan-- == 0)
657667
return nullptr;
658668

659669
--ScanFrom;
@@ -734,7 +744,7 @@ Value *llvm::FindAvailableLoadedValue(LoadInst *Load, BatchAAResults &AA,
734744
if (Inst.isDebugOrPseudoInst())
735745
continue;
736746

737-
if (MaxInstsToScan-- == 0)
747+
if (maybeAvailableLoadStore(&Inst) && MaxInstsToScan-- == 0)
738748
return nullptr;
739749

740750
Available = getAvailableLoadStore(&Inst, StrippedPtr, AccessTy,

‎llvm/test/Transforms/Coroutines/coro-retcon-resume-values.ll‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -38,15 +38,18 @@ define i32 @main() {
3838
; CHECK-NEXT: entry:
3939
; CHECK-NEXT: [[TMP0:%.*]] = tail call ptr @allocate(i32 12)
4040
; CHECK-NEXT: store i32 1, ptr [[TMP0]], align 4
41+
; CHECK-NEXT: tail call void @llvm.experimental.noalias.scope.decl(metadata [[META0:![0-9]+]])
4142
; CHECK-NEXT: [[N_VAL3_SPILL_ADDR_I:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 4
42-
; CHECK-NEXT: store i32 1, ptr [[N_VAL3_SPILL_ADDR_I]], align 4, !noalias [[META0:![0-9]+]]
43+
; CHECK-NEXT: store i32 1, ptr [[N_VAL3_SPILL_ADDR_I]], align 4, !noalias [[META0]]
4344
; CHECK-NEXT: [[INPUT_SPILL_ADDR_I:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 8
4445
; CHECK-NEXT: store i32 2, ptr [[INPUT_SPILL_ADDR_I]], align 4, !noalias [[META0]]
46+
; CHECK-NEXT: tail call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
4547
; CHECK-NEXT: [[INPUT_RELOAD_ADDR13_I:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 8
4648
; CHECK-NEXT: [[N_VAL3_RELOAD_ADDR11_I:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 4
47-
; CHECK-NEXT: store i32 3, ptr [[N_VAL3_RELOAD_ADDR11_I]], align 4, !noalias [[META3:![0-9]+]]
49+
; CHECK-NEXT: store i32 3, ptr [[N_VAL3_RELOAD_ADDR11_I]], align 4, !noalias [[META3]]
4850
; CHECK-NEXT: store i32 4, ptr [[INPUT_RELOAD_ADDR13_I]], align 4, !noalias [[META3]]
49-
; CHECK-NEXT: tail call void @print(i32 7), !noalias [[META6:![0-9]+]]
51+
; CHECK-NEXT: tail call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
52+
; CHECK-NEXT: tail call void @print(i32 7), !noalias [[META6]]
5053
; CHECK-NEXT: tail call void @deallocate(ptr nonnull [[TMP0]]), !noalias [[META6]]
5154
; CHECK-NEXT: ret i32 0
5255
;

‎llvm/test/Transforms/JumpThreading/unreachable-loops.ll‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -191,11 +191,8 @@ define i32 @constant_phi_leads_to_self_reference(ptr %ptr) {
191191
; CHECK-LABEL: @constant_phi_leads_to_self_reference(
192192
; CHECK-NEXT: [[A9:%.*]] = alloca i1, align 1
193193
; CHECK-NEXT: br label [[F6:%.*]]
194-
; CHECK: T3:
194+
; CHECK: BB5.thread:
195195
; CHECK-NEXT: br label [[BB5:%.*]]
196-
; CHECK: BB5:
197-
; CHECK-NEXT: [[L10:%.*]] = load i1, ptr [[A9]], align 1
198-
; CHECK-NEXT: br i1 [[L10]], label [[BB6:%.*]], label [[F6]]
199196
; CHECK: BB6:
200197
; CHECK-NEXT: [[LGV3:%.*]] = load i1, ptr [[PTR:%.*]], align 1
201198
; CHECK-NEXT: [[C4:%.*]] = icmp sle i1 [[C4]], true
@@ -204,7 +201,8 @@ define i32 @constant_phi_leads_to_self_reference(ptr %ptr) {
204201
; CHECK: F6:
205202
; CHECK-NEXT: ret i32 0
206203
; CHECK: F7:
207-
; CHECK-NEXT: br label [[BB5]]
204+
; CHECK-NEXT: [[L10_PR:%.*]] = load i1, ptr [[A9]], align 1
205+
; CHECK-NEXT: br i1 [[L10_PR]], label [[BB5]], label [[F6]]
208206
;
209207
%A9 = alloca i1, align 1
210208
br i1 false, label %BB4, label %F6

‎llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused.ll‎

Lines changed: 8 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -263,21 +263,17 @@ define void @multiply_reuse_load(ptr noalias %A, ptr noalias %B, ptr noalias %C)
263263
; CHECK-NEXT: store <2 x double> [[TMP7]], ptr [[C:%.*]], align 8
264264
; CHECK-NEXT: [[VEC_GEP34:%.*]] = getelementptr i8, ptr [[C]], i64 32
265265
; CHECK-NEXT: store <2 x double> [[TMP9]], ptr [[VEC_GEP34]], align 8
266-
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[A]], i64 16
267-
; CHECK-NEXT: [[COL_LOAD35:%.*]] = load <2 x double>, ptr [[TMP10]], align 8
268-
; CHECK-NEXT: [[VEC_GEP36:%.*]] = getelementptr i8, ptr [[A]], i64 48
269-
; CHECK-NEXT: [[COL_LOAD37:%.*]] = load <2 x double>, ptr [[VEC_GEP36]], align 8
270266
; CHECK-NEXT: [[COL_LOAD38:%.*]] = load <2 x double>, ptr [[A]], align 8
271267
; CHECK-NEXT: [[VEC_GEP39:%.*]] = getelementptr i8, ptr [[A]], i64 32
272268
; CHECK-NEXT: [[COL_LOAD40:%.*]] = load <2 x double>, ptr [[VEC_GEP39]], align 8
273269
; CHECK-NEXT: [[SPLAT_SPLAT43:%.*]] = shufflevector <2 x double> [[COL_LOAD38]], <2 x double> poison, <2 x i32> zeroinitializer
274-
; CHECK-NEXT: [[TMP11:%.*]] = fmul contract <2 x double> [[COL_LOAD35]], [[SPLAT_SPLAT43]]
270+
; CHECK-NEXT: [[TMP10:%.*]] = fmul contract <2 x double> [[COL_LOAD17]], [[SPLAT_SPLAT43]]
275271
; CHECK-NEXT: [[SPLAT_SPLAT46:%.*]] = shufflevector <2 x double> [[COL_LOAD38]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
276-
; CHECK-NEXT: [[TMP12:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD37]], <2 x double> [[SPLAT_SPLAT46]], <2 x double> [[TMP11]])
272+
; CHECK-NEXT: [[TMP12:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD19]], <2 x double> [[SPLAT_SPLAT46]], <2 x double> [[TMP10]])
277273
; CHECK-NEXT: [[SPLAT_SPLAT49:%.*]] = shufflevector <2 x double> [[COL_LOAD40]], <2 x double> poison, <2 x i32> zeroinitializer
278-
; CHECK-NEXT: [[TMP13:%.*]] = fmul contract <2 x double> [[COL_LOAD35]], [[SPLAT_SPLAT49]]
274+
; CHECK-NEXT: [[TMP13:%.*]] = fmul contract <2 x double> [[COL_LOAD17]], [[SPLAT_SPLAT49]]
279275
; CHECK-NEXT: [[SPLAT_SPLAT52:%.*]] = shufflevector <2 x double> [[COL_LOAD40]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
280-
; CHECK-NEXT: [[TMP14:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD37]], <2 x double> [[SPLAT_SPLAT52]], <2 x double> [[TMP13]])
276+
; CHECK-NEXT: [[TMP14:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD19]], <2 x double> [[SPLAT_SPLAT52]], <2 x double> [[TMP13]])
281277
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[A]], i64 80
282278
; CHECK-NEXT: [[COL_LOAD53:%.*]] = load <2 x double>, ptr [[TMP15]], align 8
283279
; CHECK-NEXT: [[VEC_GEP54:%.*]] = getelementptr i8, ptr [[A]], i64 112
@@ -313,22 +309,18 @@ define void @multiply_reuse_load(ptr noalias %A, ptr noalias %B, ptr noalias %C)
313309
; CHECK-NEXT: [[TMP25:%.*]] = fmul contract <2 x double> [[COL_LOAD74]], [[SPLAT_SPLAT88]]
314310
; CHECK-NEXT: [[SPLAT_SPLAT91:%.*]] = shufflevector <2 x double> [[COL_LOAD79]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
315311
; CHECK-NEXT: [[TMP26:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD76]], <2 x double> [[SPLAT_SPLAT91]], <2 x double> [[TMP25]])
316-
; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[A]], i64 64
317-
; CHECK-NEXT: [[COL_LOAD92:%.*]] = load <2 x double>, ptr [[TMP27]], align 8
318-
; CHECK-NEXT: [[VEC_GEP93:%.*]] = getelementptr i8, ptr [[A]], i64 96
319-
; CHECK-NEXT: [[COL_LOAD94:%.*]] = load <2 x double>, ptr [[VEC_GEP93]], align 8
320312
; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[A]], i64 80
321313
; CHECK-NEXT: [[COL_LOAD95:%.*]] = load <2 x double>, ptr [[TMP28]], align 8
322314
; CHECK-NEXT: [[VEC_GEP96:%.*]] = getelementptr i8, ptr [[A]], i64 112
323315
; CHECK-NEXT: [[COL_LOAD97:%.*]] = load <2 x double>, ptr [[VEC_GEP96]], align 8
324316
; CHECK-NEXT: [[SPLAT_SPLAT101:%.*]] = shufflevector <2 x double> [[COL_LOAD95]], <2 x double> poison, <2 x i32> zeroinitializer
325-
; CHECK-NEXT: [[TMP29:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD92]], <2 x double> [[SPLAT_SPLAT101]], <2 x double> [[TMP24]])
317+
; CHECK-NEXT: [[TMP27:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD77]], <2 x double> [[SPLAT_SPLAT101]], <2 x double> [[TMP24]])
326318
; CHECK-NEXT: [[SPLAT_SPLAT104:%.*]] = shufflevector <2 x double> [[COL_LOAD95]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
327-
; CHECK-NEXT: [[TMP30:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD94]], <2 x double> [[SPLAT_SPLAT104]], <2 x double> [[TMP29]])
319+
; CHECK-NEXT: [[TMP30:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD79]], <2 x double> [[SPLAT_SPLAT104]], <2 x double> [[TMP27]])
328320
; CHECK-NEXT: [[SPLAT_SPLAT108:%.*]] = shufflevector <2 x double> [[COL_LOAD97]], <2 x double> poison, <2 x i32> zeroinitializer
329-
; CHECK-NEXT: [[TMP31:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD92]], <2 x double> [[SPLAT_SPLAT108]], <2 x double> [[TMP26]])
321+
; CHECK-NEXT: [[TMP29:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD77]], <2 x double> [[SPLAT_SPLAT108]], <2 x double> [[TMP26]])
330322
; CHECK-NEXT: [[SPLAT_SPLAT111:%.*]] = shufflevector <2 x double> [[COL_LOAD97]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
331-
; CHECK-NEXT: [[TMP32:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD94]], <2 x double> [[SPLAT_SPLAT111]], <2 x double> [[TMP31]])
323+
; CHECK-NEXT: [[TMP32:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD79]], <2 x double> [[SPLAT_SPLAT111]], <2 x double> [[TMP29]])
332324
; CHECK-NEXT: [[TMP33:%.*]] = getelementptr i8, ptr [[C]], i64 64
333325
; CHECK-NEXT: store <2 x double> [[TMP30]], ptr [[TMP33]], align 8
334326
; CHECK-NEXT: [[VEC_GEP112:%.*]] = getelementptr i8, ptr [[C]], i64 96

‎llvm/test/Transforms/PhaseOrdering/early-arg-attrs-inference.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33

44
define i32 @f(ptr noalias %p, i32 %c) {
55
; CHECK-LABEL: define noundef i32 @f
6-
; CHECK-SAME: (ptr noalias readonly captures(none) [[P:%.*]], i32 [[C:%.*]]) local_unnamed_addr {
6+
; CHECK-SAME: (ptr noalias readnone captures(none) [[P:%.*]], i32 [[C:%.*]]) local_unnamed_addr {
77
; CHECK-NEXT: tail call void @g()
88
; CHECK-NEXT: tail call void @g()
99
; CHECK-NEXT: tail call void @g()

‎llvm/test/Transforms/PhaseOrdering/pr137810-forward-load.ll‎

Lines changed: 3 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1,37 +1,16 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
22
; RUN: opt -O2 -S < %s | FileCheck %s
33

4-
; FIXME: It can return true.
54
define i1 @main(ptr %i2) {
65
; CHECK-LABEL: define noundef i1 @main(
7-
; CHECK-SAME: ptr captures(none) initializes((0, 3)) [[I2:%.*]]) local_unnamed_addr {
8-
; CHECK-NEXT: [[I1:%.*]] = alloca [3 x i8], align 1
6+
; CHECK-SAME: ptr writeonly captures(none) initializes((0, 3)) [[I2:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
7+
; CHECK-NEXT: [[TRUE:.*:]]
98
; CHECK-NEXT: store i8 0, ptr [[I2]], align 1
109
; CHECK-NEXT: [[I3:%.*]] = getelementptr inbounds nuw i8, ptr [[I2]], i64 1
1110
; CHECK-NEXT: store i8 1, ptr [[I3]], align 1
1211
; CHECK-NEXT: [[I4:%.*]] = getelementptr inbounds nuw i8, ptr [[I2]], i64 2
1312
; CHECK-NEXT: store i8 2, ptr [[I4]], align 1
14-
; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 3, ptr nonnull [[I1]])
15-
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 1 dereferenceable(3) [[I1]], ptr noundef nonnull align 1 dereferenceable(3) [[I2]], i64 3, i1 false)
16-
; CHECK-NEXT: [[I51:%.*]] = load i8, ptr [[I2]], align 1
17-
; CHECK-NEXT: [[I6:%.*]] = icmp eq i8 [[I51]], 0
18-
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr [[I2]], i64 1
19-
; CHECK-NEXT: [[I82:%.*]] = load i8, ptr [[TMP1]], align 1
20-
; CHECK-NEXT: [[I9:%.*]] = icmp eq i8 [[I82]], 1
21-
; CHECK-NEXT: [[I10:%.*]] = select i1 [[I6]], i1 [[I9]], i1 false
22-
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw i8, ptr [[I2]], i64 2
23-
; CHECK-NEXT: [[I123:%.*]] = load i8, ptr [[TMP2]], align 1
24-
; CHECK-NEXT: [[I13:%.*]] = icmp eq i8 [[I123]], 2
25-
; CHECK-NEXT: [[I14:%.*]] = select i1 [[I10]], i1 [[I13]], i1 false
26-
; CHECK-NEXT: br i1 [[I14]], label %[[TRUE:.*]], label %[[FALSE:.*]]
27-
; CHECK: [[COMMON_RET:.*]]:
28-
; CHECK-NEXT: ret i1 [[I14]]
29-
; CHECK: [[TRUE]]:
30-
; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 3, ptr nonnull [[I1]])
31-
; CHECK-NEXT: br label %[[COMMON_RET]]
32-
; CHECK: [[FALSE]]:
33-
; CHECK-NEXT: call void @assert_failed(ptr nonnull [[I1]])
34-
; CHECK-NEXT: br label %[[COMMON_RET]]
13+
; CHECK-NEXT: ret i1 true
3514
;
3615
%i1 = alloca [3 x i8], align 1
3716
store i8 0, ptr %i2, align 1

‎llvm/test/Transforms/SLPVectorizer/revec-shufflevector.ll‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -231,14 +231,13 @@ define void @test6(ptr %in0, ptr %in1, ptr %in2) {
231231
; COMBINE-NEXT: [[TMP7:%.*]] = fmul <32 x float> [[TMP6]], [[TMP2]]
232232
; COMBINE-NEXT: [[GEP10:%.*]] = getelementptr inbounds nuw i8, ptr [[IN1]], i64 32
233233
; COMBINE-NEXT: [[GEP11:%.*]] = getelementptr inbounds nuw i8, ptr [[IN2:%.*]], i64 128
234-
; COMBINE-NEXT: [[TMP8:%.*]] = load <8 x float>, ptr [[IN0]], align 16
235234
; COMBINE-NEXT: store <32 x float> [[TMP7]], ptr [[IN2]], align 16
236235
; COMBINE-NEXT: [[LOAD5:%.*]] = load <16 x i8>, ptr [[GEP10]], align 1
237236
; COMBINE-NEXT: [[TMP9:%.*]] = uitofp <16 x i8> [[LOAD5]] to <16 x float>
238237
; COMBINE-NEXT: [[TMP10:%.*]] = shufflevector <4 x float> [[LOAD2]], <4 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
239-
; COMBINE-NEXT: [[TMP11:%.*]] = shufflevector <8 x float> [[TMP8]], <8 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
238+
; COMBINE-NEXT: [[TMP11:%.*]] = shufflevector <8 x float> [[TMP0]], <8 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
240239
; COMBINE-NEXT: [[TMP12:%.*]] = shufflevector <16 x float> [[TMP10]], <16 x float> [[TMP11]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
241-
; COMBINE-NEXT: [[TMP13:%.*]] = shufflevector <8 x float> [[TMP8]], <8 x float> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
240+
; COMBINE-NEXT: [[TMP13:%.*]] = shufflevector <8 x float> [[TMP0]], <8 x float> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
242241
; COMBINE-NEXT: [[TMP14:%.*]] = shufflevector <4 x float> [[TMP13]], <4 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
243242
; COMBINE-NEXT: [[TMP15:%.*]] = shufflevector <16 x float> [[TMP12]], <16 x float> [[TMP14]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 poison, i32 poison, i32 poison, i32 poison>
244243
; COMBINE-NEXT: [[TMP16:%.*]] = shufflevector <16 x float> [[TMP15]], <16 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 0, i32 1, i32 2, i32 3>

‎llvm/test/Transforms/SampleProfile/pseudo-probe-instcombine.ll‎

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -106,6 +106,56 @@ define i32 @load(ptr nocapture %a, ptr nocapture %b) {
106106
ret i32 %5
107107
}
108108

109+
;; Check the load is deleted.
110+
define i32 @load_not_pseudo(ptr noalias %arg, ptr noalias %arg1) {
111+
; CHECK-LABEL: @load_not_pseudo(
112+
; CHECK-NEXT: bb:
113+
; CHECK-NEXT: store i32 1, ptr [[ARG1:%.*]], align 4
114+
; CHECK-NEXT: store i32 1, ptr [[ARG2:%.*]], align 4
115+
; CHECK-NEXT: ret i32 1
116+
;
117+
bb:
118+
store i32 1, ptr %arg, align 4
119+
store i32 1, ptr %arg1, align 4
120+
%i = load i32, ptr %arg, align 4
121+
ret i32 %i
122+
}
123+
124+
;; Check the load is deleted.
125+
define i32 @load_not_pseudo_2(ptr noalias %arg, ptr noalias %arg1) {
126+
; CHECK-LABEL: @load_not_pseudo_2(
127+
; CHECK-NEXT: bb:
128+
; CHECK-NEXT: store i32 1, ptr [[ARG:%.*]], align 4
129+
; CHECK-NEXT: [[ARG1_1:%.*]] = getelementptr inbounds nuw i8, ptr [[ARG1:%.*]], i64 4
130+
; CHECK-NEXT: store i32 1, ptr [[ARG1_1]], align 4
131+
; CHECK-NEXT: ret i32 1
132+
;
133+
bb:
134+
store i32 1, ptr %arg, align 4
135+
%arg1_1 = getelementptr inbounds i32, ptr %arg1, i32 1
136+
store i32 1, ptr %arg1_1, align 4
137+
%i = load i32, ptr %arg, align 4
138+
ret i32 %i
139+
}
140+
141+
;; Check the load is not deleted.
142+
define i32 @load_not_pseudo_3(ptr noalias %arg, ptr noalias %arg1, ptr noalias %arg2) {
143+
; CHECK-LABEL: @load_not_pseudo_3(
144+
; CHECK-NEXT: bb:
145+
; CHECK-NEXT: store i32 1, ptr [[ARG:%.*]], align 4
146+
; CHECK-NEXT: store i32 1, ptr [[ARG1:%.*]], align 4
147+
; CHECK-NEXT: store i32 1, ptr [[ARG2:%.*]], align 4
148+
; CHECK-NEXT: [[I:%.*]] = load i32, ptr [[ARG]], align 4
149+
; CHECK-NEXT: ret i32 [[I]]
150+
;
151+
bb:
152+
store i32 1, ptr %arg, align 4
153+
store i32 1, ptr %arg1, align 4
154+
store i32 1, ptr %arg2, align 4
155+
%i = load i32, ptr %arg, align 4
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ret i32 %i
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}
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109159
;; Check the first store is deleted.
110160
define void @dse(ptr %p) {
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; CHECK-LABEL: @dse(

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