Remove the Alpha backend.

llvm-svn: 143164

llvm/CMakeLists.txt

@@ -64,7 +64,6 @@ Please clean the source directory.")
 endif()
 
 set(LLVM_ALL_TARGETS
-  Alpha
   ARM
   CBackend
   CellSPU

llvm/autoconf/configure.ac

@@ -352,7 +352,6 @@ AC_CACHE_CHECK([target architecture],[llvm_cv_target_arch],
   amd64-* | x86_64-*)     llvm_cv_target_arch="x86_64" ;;
   sparc*-*)               llvm_cv_target_arch="Sparc" ;;
   powerpc*-*)             llvm_cv_target_arch="PowerPC" ;;
-  alpha*-*)               llvm_cv_target_arch="Alpha" ;;
   arm*-*)                 llvm_cv_target_arch="ARM" ;;
   mips-*)                 llvm_cv_target_arch="Mips" ;;
   xcore-*)                llvm_cv_target_arch="XCore" ;;
@@ -487,7 +486,6 @@ else
     Sparc)       AC_SUBST(TARGET_HAS_JIT,0) ;;
     PowerPC)     AC_SUBST(TARGET_HAS_JIT,1) ;;
     x86_64)      AC_SUBST(TARGET_HAS_JIT,1) ;;
-    Alpha)       AC_SUBST(TARGET_HAS_JIT,0) ;;
     ARM)         AC_SUBST(TARGET_HAS_JIT,1) ;;
     Mips)        AC_SUBST(TARGET_HAS_JIT,1) ;;
     XCore)       AC_SUBST(TARGET_HAS_JIT,0) ;;
@@ -603,21 +601,20 @@ dnl Allow specific targets to be specified for building (or not)
 TARGETS_TO_BUILD=""
 AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
     [Build specific host targets: all or target1,target2,... Valid targets are:
-     host, x86, x86_64, sparc, powerpc, alpha, arm, mips, spu,
+     host, x86, x86_64, sparc, powerpc, arm, mips, spu,
      xcore, msp430, ptx, cbe, and cpp (default=all)]),,
     enableval=all)
 if test "$enableval" = host-only ; then
   enableval=host
 fi
 case "$enableval" in
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
   *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
       case "$a_target" in
         x86)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
         x86_64)   TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
         sparc)    TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
         powerpc)  TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
-        alpha)    TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
         arm)      TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
         mips)     TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
         spu)      TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
@@ -632,7 +629,6 @@ case "$enableval" in
             x86_64)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
             Sparc)       TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
             PowerPC)     TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
-            Alpha)       TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
             ARM)         TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
             Mips)        TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
             MBlaze)      TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;

llvm/cmake/config-ix.cmake

@@ -309,8 +309,6 @@ elseif (LLVM_NATIVE_ARCH MATCHES "sparc")
   set(LLVM_NATIVE_ARCH Sparc)
 elseif (LLVM_NATIVE_ARCH MATCHES "powerpc")
   set(LLVM_NATIVE_ARCH PowerPC)
-elseif (LLVM_NATIVE_ARCH MATCHES "alpha")
-  set(LLVM_NATIVE_ARCH Alpha)
 elseif (LLVM_NATIVE_ARCH MATCHES "arm")
   set(LLVM_NATIVE_ARCH ARM)
 elseif (LLVM_NATIVE_ARCH MATCHES "mips")

llvm/configure

@@ -1415,7 +1415,7 @@ Optional Features:
                           (default is YES)
   --enable-targets        Build specific host targets: all or
                           target1,target2,... Valid targets are: host, x86,
-                          x86_64, sparc, powerpc, alpha, arm, mips, spu,
+                          x86_64, sparc, powerpc, arm, mips, spu,
                           xcore, msp430, ptx, cbe, and cpp (default=all)
   --enable-cbe-printf-a   Enable C Backend output with hex floating point via
                           %a (default is YES)
@@ -3874,7 +3874,6 @@ else
   amd64-* | x86_64-*)     llvm_cv_target_arch="x86_64" ;;
   sparc*-*)               llvm_cv_target_arch="Sparc" ;;
   powerpc*-*)             llvm_cv_target_arch="PowerPC" ;;
-  alpha*-*)               llvm_cv_target_arch="Alpha" ;;
   arm*-*)                 llvm_cv_target_arch="ARM" ;;
   mips-*)                 llvm_cv_target_arch="Mips" ;;
   xcore-*)                llvm_cv_target_arch="XCore" ;;
@@ -5071,8 +5070,6 @@ else
     PowerPC)     TARGET_HAS_JIT=1
  ;;
     x86_64)      TARGET_HAS_JIT=1
- ;;
-    Alpha)       TARGET_HAS_JIT=0
  ;;
     ARM)         TARGET_HAS_JIT=1
  ;;
@@ -5270,14 +5267,13 @@ if test "$enableval" = host-only ; then
   enableval=host
 fi
 case "$enableval" in
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
   *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
       case "$a_target" in
         x86)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
         x86_64)   TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
         sparc)    TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
         powerpc)  TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
-        alpha)    TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
         arm)      TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
         mips)     TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
         spu)      TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
@@ -5292,7 +5288,6 @@ case "$enableval" in
             x86_64)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
             Sparc)       TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
             PowerPC)     TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
-            Alpha)       TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
             ARM)         TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
             Mips)        TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
             MBlaze)      TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;

llvm/docs/CMake.html

@@ -249,7 +249,7 @@ <h3>
   <dd>Semicolon-separated list of targets to build, or <i>all</i> for
     building all targets. Case-sensitive. For Visual C++ defaults
     to <i>X86</i>. On the other cases defaults to <i>all</i>. Example:
-    <i>-DLLVM_TARGETS_TO_BUILD="X86;PowerPC;Alpha"</i>.</dd>
+    <i>-DLLVM_TARGETS_TO_BUILD="X86;PowerPC"</i>.</dd>
 
   <dt><b>LLVM_BUILD_TOOLS</b>:BOOL</dt>
   <dd>Build LLVM tools. Defaults to ON. Targets for building each tool

llvm/docs/CodeGenerator.html

@@ -2208,7 +2208,6 @@ <h3>
   <tr>
     <th>Feature</th>
     <th>ARM</th>
-    <th>Alpha</th>
     <th>CellSPU</th>
     <th>MBlaze</th>
     <th>MSP430</th>
@@ -2223,7 +2222,6 @@ <h3>
 <tr>
   <td><a href="#feat_reliable">is generally reliable</a></td>
   <td class="yes"></td> <!-- ARM -->
-  <td class="unknown"></td> <!-- Alpha -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
@@ -2238,7 +2236,6 @@ <h3>
 <tr>
   <td><a href="#feat_asmparser">assembly parser</a></td>
   <td class="no"></td> <!-- ARM -->
-  <td class="no"></td> <!-- Alpha -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="yes"></td> <!-- MBlaze -->
   <td class="no"></td> <!-- MSP430 -->
@@ -2253,7 +2250,6 @@ <h3>
 <tr>
   <td><a href="#feat_disassembler">disassembler</a></td>
   <td class="yes"></td> <!-- ARM -->
-  <td class="no"></td> <!-- Alpha -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="yes"></td> <!-- MBlaze -->
   <td class="no"></td> <!-- MSP430 -->
@@ -2268,7 +2264,6 @@ <h3>
 <tr>
   <td><a href="#feat_inlineasm">inline asm</a></td>
   <td class="yes"></td> <!-- ARM -->
-  <td class="unknown"></td> <!-- Alpha -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="yes"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
@@ -2283,7 +2278,6 @@ <h3>
 <tr>
   <td><a href="#feat_jit">jit</a></td>
   <td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->
-  <td class="no"></td> <!-- Alpha -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->
@@ -2298,7 +2292,6 @@ <h3>
 <tr>
   <td><a href="#feat_objectwrite">.o&nbsp;file writing</a></td>
   <td class="no"></td> <!-- ARM -->
-  <td class="no"></td> <!-- Alpha -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="yes"></td> <!-- MBlaze -->
   <td class="no"></td> <!-- MSP430 -->
@@ -2313,7 +2306,6 @@ <h3>
 <tr>
   <td><a href="#feat_tailcall">tail calls</a></td>
   <td class="yes"></td> <!-- ARM -->
-  <td class="unknown"></td> <!-- Alpha -->
   <td class="no"></td> <!-- CellSPU -->
   <td class="no"></td> <!-- MBlaze -->
   <td class="unknown"></td> <!-- MSP430 -->

llvm/docs/CompilerWriterInfo.html

@@ -21,7 +21,6 @@ <h1>
 <ol>
   <li><a href="#hw">Hardware</a>
   <ol>
-    <li><a href="#alpha">Alpha</a></li>
     <li><a href="#arm">ARM</a></li>
     <li><a href="#ia64">Itanium</a></li>
     <li><a href="#mips">MIPS</a></li>
@@ -48,17 +47,6 @@ <h2><a name="hw">Hardware</a></h2>
 
 <div>
 
-<!-- ======================================================================= -->
-<h3><a name="alpha">Alpha</a></h3>
-
-<div>
-<ul>
-<li><a
-href="http://ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html">Alpha manuals</a> 
-</li>
-</ul>
-</div>
-
 <!-- ======================================================================= -->
 <h3><a name="arm">ARM</a></h3>
 

llvm/docs/UsingLibraries.html

@@ -126,8 +126,6 @@ <h2><a name="descriptions">Library Descriptions</a></h2>
     <td>Aggressive instruction selector for directed acyclic graphs</td></tr>
 
   <tr><th colspan="3">Target Libraries</th></tr>
-  <tr><td>LLVMAlpha</td><td><tt>.o</tt></td>
-    <td>Code generation for Alpha architecture</td></tr>
   <tr><td>LLVMARM</td><td><tt>.o</tt></td>
     <td>Code generation for ARM architecture</td></tr>
   <tr><td>LLVMCBackend</td><td><tt>.o</tt></td>
@@ -333,14 +331,6 @@ <h3>Dependency Relationships Of Object Files</h3>
     <li>libLLVMSystem.a</li>
     <li>libLLVMTarget.a</li>
   </ul></dd>
-  <dt><b>LLVMAlpha.o</b></dt><dd><ul>
-    <li>libLLVMCodeGen.a</li>
-    <li>libLLVMCore.a</li>
-    <li>libLLVMSelectionDAG.a</li>
-    <li>libLLVMSupport.a</li>
-    <li>libLLVMSystem.a</li>
-    <li>libLLVMTarget.a</li>
-  </ul></dd>
   <dt><b>LLVMCBackend.o</b></dt><dd><ul>
     <li>libLLVMAnalysis.a</li>
     <li>libLLVMCodeGen.a</li>

llvm/include/llvm/ADT/Triple.h

@@ -43,7 +43,6 @@ class Triple {
   enum ArchType {
     UnknownArch,
 
-    alpha,   // Alpha: alpha
     arm,     // ARM; arm, armv.*, xscale
     cellspu, // CellSPU: spu, cellspu
     mips,    // MIPS: mips, mipsallegrex

llvm/include/llvm/Intrinsics.td

@@ -443,6 +443,5 @@ include "llvm/IntrinsicsPowerPC.td"
 include "llvm/IntrinsicsX86.td"
 include "llvm/IntrinsicsARM.td"
 include "llvm/IntrinsicsCellSPU.td"
-include "llvm/IntrinsicsAlpha.td"
 include "llvm/IntrinsicsXCore.td"
 include "llvm/IntrinsicsPTX.td"

llvm/lib/Support/Triple.cpp

@@ -18,7 +18,6 @@ const char *Triple::getArchTypeName(ArchType Kind) {
   case InvalidArch: return "<invalid>";
   case UnknownArch: return "unknown";
 
-  case alpha:   return "alpha";
   case arm:     return "arm";
   case cellspu: return "cellspu";
   case mips:    return "mips";
@@ -50,8 +49,6 @@ const char *Triple::getArchTypePrefix(ArchType Kind) {
   default:
     return 0;
 
-  case alpha:   return "alpha";
-
   case arm:
   case thumb:   return "arm";
 
@@ -131,8 +128,6 @@ const char *Triple::getEnvironmentTypeName(EnvironmentType Kind) {
 }
 
 Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
-  if (Name == "alpha")
-    return alpha;
   if (Name == "arm")
     return arm;
   if (Name == "cellspu")
@@ -286,8 +281,6 @@ Triple::ArchType Triple::ParseArch(StringRef ArchName) {
   else if (ArchName == "thumb" ||
            ArchName.startswith("thumbv"))
     return thumb;
-  else if (ArchName.startswith("alpha"))
-    return alpha;
   else if (ArchName == "spu" || ArchName == "cellspu")
     return cellspu;
   else if (ArchName == "msp430")