Address comments

- More consistent .td
- Clearer comment in AArch64ExpandPseudoInsts.cpp

Author: gbossu

llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

@@ -529,7 +529,8 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
     }
     break;
   case AArch64::Destructive2xRegImmUnpred:
-    // EXT_ZZI_CONSTRUCTIVE Zd, Zs, Imm ==> EXT_ZZI Zds, Zds, Zds, Imm
+    // EXT_ZZI_CONSTRUCTIVE Zd, Zs, Imm
+    //      ==> MOVPRFX Zd Zs; EXT_ZZI Zd, Zd, Zs, Imm
     std::tie(DOPIdx, SrcIdx, Src2Idx) = std::make_tuple(1, 1, 2);
     break;
   default:

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

@@ -1023,7 +1023,7 @@ let Predicates = [HasSVE_or_SME] in {
   defm INSR_ZV : sve_int_perm_insrv<"insr", AArch64insr>;
   defm EXT_ZZI : sve_int_perm_extract_i<"ext", AArch64ext, "EXT_ZZI_CONSTRUCTIVE">;
 
-  def EXT_ZZI_CONSTRUCTIVE : UnpredRegImmPseudo<"EXT_ZZI_CONSTRUCTIVE", ZPR8, imm0_255>;
+  def EXT_ZZI_CONSTRUCTIVE : UnpredRegImmPseudo<ZPR8, imm0_255>;
 
   defm RBIT_ZPmZ : sve_int_perm_rev_rbit<"rbit", AArch64rbit_mt>;
   defm REVB_ZPmZ : sve_int_perm_rev_revb<"revb", AArch64revb_mt>;

llvm/lib/Target/AArch64/SVEInstrFormats.td

@@ -810,8 +810,8 @@ let hasNoSchedulingInfo = 1 in {
     let FalseLanes = flags;
   }
 
-  class UnpredRegImmPseudo<string name, ZPRRegOp zprty, Operand immty>
-  : SVEPseudo2Instr<name, 0>,
+  class UnpredRegImmPseudo<ZPRRegOp zprty, Operand immty>
+  : SVEPseudo2Instr<NAME, 0>,
     Pseudo<(outs zprty:$Zd), (ins zprty:$Zs, immty:$imm), []> {
   }
 }
@@ -1895,9 +1895,9 @@ class sve_int_perm_extract_i<string asm>
   let hasSideEffects = 0;
 }
 
-multiclass sve_int_perm_extract_i<string asm, SDPatternOperator op, string pseudoInstrName> {
+multiclass sve_int_perm_extract_i<string asm, SDPatternOperator op, string Ps> {
   def NAME : sve_int_perm_extract_i<asm>,
-             SVEPseudo2Instr<pseudoInstrName, 1>;
+             SVEPseudo2Instr<Ps, 1>;
 
   def : SVE_3_Op_Imm_Pat<nxv16i8, op, nxv16i8, nxv16i8, i32, imm0_255,
                          !cast<Instruction>(NAME)>;