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[ConstantFolding] Generalize constant folding for vector_interleave2 to interleave3-8.
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+20
-14
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2 files changed

+20
-14
lines changed

‎llvm/lib/Analysis/ConstantFolding.cpp‎

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1659,6 +1659,12 @@ bool llvm::canConstantFoldCallTo(const CallBase *Call, const Function *F) {
16591659
case Intrinsic::vector_extract:
16601660
case Intrinsic::vector_insert:
16611661
case Intrinsic::vector_interleave2:
1662+
case Intrinsic::vector_interleave3:
1663+
case Intrinsic::vector_interleave4:
1664+
case Intrinsic::vector_interleave5:
1665+
case Intrinsic::vector_interleave6:
1666+
case Intrinsic::vector_interleave7:
1667+
case Intrinsic::vector_interleave8:
16621668
case Intrinsic::vector_deinterleave2:
16631669
// Target intrinsics
16641670
case Intrinsic::amdgcn_perm:
@@ -4207,12 +4213,18 @@ static Constant *ConstantFoldFixedVectorCall(
42074213
}
42084214
return ConstantVector::get(Result);
42094215
}
4210-
case Intrinsic::vector_interleave2: {
4216+
case Intrinsic::vector_interleave2:
4217+
case Intrinsic::vector_interleave3:
4218+
case Intrinsic::vector_interleave4:
4219+
case Intrinsic::vector_interleave5:
4220+
case Intrinsic::vector_interleave6:
4221+
case Intrinsic::vector_interleave7:
4222+
case Intrinsic::vector_interleave8: {
42114223
unsigned NumElements =
42124224
cast<FixedVectorType>(Operands[0]->getType())->getNumElements();
42134225
unsigned NumOperands = Operands.size();
42144226
for (unsigned I = 0; I < NumElements; ++I) {
4215-
for (unsigned J = 0, JE = NumOperands; J != JE; ++J) {
4227+
for (unsigned J = 0; J < NumOperands; ++J) {
42164228
Constant *Elt = Operands[J]->getAggregateElement(I);
42174229
if (!Elt)
42184230
return nullptr;

‎llvm/test/Transforms/InstSimplify/ConstProp/vector-calls.ll‎

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -53,53 +53,47 @@ define <8 x i32> @fold_vector_interleave2() {
5353

5454
define <12 x i32> @fold_vector_interleave3() {
5555
; CHECK-LABEL: define <12 x i32> @fold_vector_interleave3() {
56-
; CHECK-NEXT: [[TMP1:%.*]] = call <12 x i32> @llvm.vector.interleave3.v12i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> <i32 9, i32 10, i32 11, i32 12>)
57-
; CHECK-NEXT: ret <12 x i32> [[TMP1]]
56+
; CHECK-NEXT: ret <12 x i32> <i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11, i32 4, i32 8, i32 12>
5857
;
5958
%1 = call <12 x i32> @llvm.vector.interleave3.v12i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> <i32 9, i32 10, i32 11, i32 12>)
6059
ret <12 x i32> %1
6160
}
6261

6362
define <16 x i32> @fold_vector_interleave4() {
6463
; CHECK-LABEL: define <16 x i32> @fold_vector_interleave4() {
65-
; CHECK-NEXT: [[TMP1:%.*]] = call <16 x i32> @llvm.vector.interleave4.v16i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> <i32 9, i32 10, i32 11, i32 12>, <4 x i32> <i32 13, i32 14, i32 15, i32 16>)
66-
; CHECK-NEXT: ret <16 x i32> [[TMP1]]
64+
; CHECK-NEXT: ret <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15, i32 4, i32 8, i32 12, i32 16>
6765
;
6866
%1 = call <16 x i32> @llvm.vector.interleave4.v16i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> <i32 9, i32 10, i32 11, i32 12>, <4 x i32> <i32 13, i32 14, i32 15, i32 16>)
6967
ret <16 x i32> %1
7068
}
7169

7270
define <20 x i32> @fold_vector_interleave5() {
7371
; CHECK-LABEL: define <20 x i32> @fold_vector_interleave5() {
74-
; CHECK-NEXT: [[TMP1:%.*]] = call <20 x i32> @llvm.vector.interleave5.v20i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> <i32 9, i32 10, i32 11, i32 12>, <4 x i32> <i32 13, i32 14, i32 15, i32 16>, <4 x i32> <i32 17, i32 18, i32 19, i32 20>)
75-
; CHECK-NEXT: ret <20 x i32> [[TMP1]]
72+
; CHECK-NEXT: ret <20 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 2, i32 6, i32 10, i32 14, i32 18, i32 3, i32 7, i32 11, i32 15, i32 19, i32 4, i32 8, i32 12, i32 16, i32 20>
7673
;
7774
%1 = call <20 x i32> @llvm.vector.interleave5.v20i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> <i32 9, i32 10, i32 11, i32 12>, <4 x i32> <i32 13, i32 14, i32 15, i32 16>, <4 x i32> <i32 17, i32 18, i32 19, i32 20>)
7875
ret <20 x i32> %1
7976
}
8077

8178
define <24 x i32> @fold_vector_interleave6() {
8279
; CHECK-LABEL: define <24 x i32> @fold_vector_interleave6() {
83-
; CHECK-NEXT: [[TMP1:%.*]] = call <24 x i32> @llvm.vector.interleave6.v24i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> <i32 9, i32 10, i32 11, i32 12>, <4 x i32> <i32 13, i32 14, i32 15, i32 16>, <4 x i32> <i32 17, i32 18, i32 19, i32 20>, <4 x i32> <i32 21, i32 22, i32 23, i32 24>)
84-
; CHECK-NEXT: ret <24 x i32> [[TMP1]]
80+
; CHECK-NEXT: ret <24 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24>
8581
;
8682
%1 = call <24 x i32> @llvm.vector.interleave6.v24i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> <i32 9, i32 10, i32 11, i32 12>, <4 x i32> <i32 13, i32 14, i32 15, i32 16>, <4 x i32> <i32 17, i32 18, i32 19, i32 20>, <4 x i32> <i32 21, i32 22, i32 23, i32 24>)
8783
ret <24 x i32> %1
8884
}
8985

9086
define <28 x i32> @fold_vector_interleave7() {
9187
; CHECK-LABEL: define <28 x i32> @fold_vector_interleave7() {
92-
; CHECK-NEXT: [[TMP1:%.*]] = call <28 x i32> @llvm.vector.interleave7.v28i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> <i32 9, i32 10, i32 11, i32 12>, <4 x i32> <i32 13, i32 14, i32 15, i32 16>, <4 x i32> <i32 17, i32 18, i32 19, i32 20>, <4 x i32> <i32 21, i32 22, i32 23, i32 24>, <4 x i32> <i32 25, i32 26, i32 27, i32 28>)
93-
; CHECK-NEXT: ret <28 x i32> [[TMP1]]
88+
; CHECK-NEXT: ret <28 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
9489
;
9590
%1 = call <28 x i32> @llvm.vector.interleave7.v28i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> <i32 9, i32 10, i32 11, i32 12>, <4 x i32> <i32 13, i32 14, i32 15, i32 16>, <4 x i32> <i32 17, i32 18, i32 19, i32 20>, <4 x i32> <i32 21, i32 22, i32 23, i32 24>, <4 x i32> <i32 25, i32 26, i32 27, i32 28>)
9691
ret <28 x i32> %1
9792
}
9893

9994
define <32 x i32> @fold_vector_interleave8() {
10095
; CHECK-LABEL: define <32 x i32> @fold_vector_interleave8() {
101-
; CHECK-NEXT: [[TMP1:%.*]] = call <32 x i32> @llvm.vector.interleave8.v32i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> <i32 9, i32 10, i32 11, i32 12>, <4 x i32> <i32 13, i32 14, i32 15, i32 16>, <4 x i32> <i32 17, i32 18, i32 19, i32 20>, <4 x i32> <i32 21, i32 22, i32 23, i32 24>, <4 x i32> <i32 25, i32 26, i32 27, i32 28>, <4 x i32> <i32 29, i32 30, i32 31, i32 32>)
102-
; CHECK-NEXT: ret <32 x i32> [[TMP1]]
96+
; CHECK-NEXT: ret <32 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32>
10397
;
10498
%1 = call <32 x i32> @llvm.vector.interleave8.v32i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> <i32 9, i32 10, i32 11, i32 12>, <4 x i32> <i32 13, i32 14, i32 15, i32 16>, <4 x i32> <i32 17, i32 18, i32 19, i32 20>, <4 x i32> <i32 21, i32 22, i32 23, i32 24>, <4 x i32> <i32 25, i32 26, i32 27, i32 28>, <4 x i32> <i32 29, i32 30, i32 31, i32 32>)
10599
ret <32 x i32> %1

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