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Revert "[X86] Separate imm from relocImm handling."
> relocImm was a complexPattern that handled both ConstantSDNode > and X86Wrapper. But it was only applied selectively because using > it would cause patterns to be not importable into FastISel or > GlobalISel. So it only got applied to flag setting instructions, > stores, RMW arithmetic instructions, and rotates. > > Most of the test changes are a result of making patterns available > to GlobalISel or FastISel. The absolute-cmp.ll change is due to > this fixing a pattern ordering issue to make an absolute symbol > match to an 8-bit immediate before trying a 32-bit immediate. > > I tried to use PatFrags to reduce the repetition, but I was getting > errors from TableGen. This caused "Invalid EmitNode" assertions, see the llvm-commits thread for discussion.
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‎llvm/lib/Target/X86/X86ISelDAGToDAG.cpp‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -472,6 +472,14 @@ namespace {
472472

473473
bool isSExtAbsoluteSymbolRef(unsigned Width, SDNode *N) const;
474474

475+
/// Returns whether this is a relocatable immediate in the range
476+
/// [-2^Width .. 2^Width-1].
477+
template <unsigned Width> bool isSExtRelocImm(SDNode *N) const {
478+
if (auto *CN = dyn_cast<ConstantSDNode>(N))
479+
return isInt<Width>(CN->getSExtValue());
480+
return isSExtAbsoluteSymbolRef(Width, N);
481+
}
482+
475483
// Indicates we should prefer to use a non-temporal load for this load.
476484
bool useNonTemporalLoad(LoadSDNode *N) const {
477485
if (!N->isNonTemporal())
@@ -2643,6 +2651,12 @@ bool X86DAGToDAGISel::selectTLSADDRAddr(SDValue N, SDValue &Base,
26432651
}
26442652

26452653
bool X86DAGToDAGISel::selectRelocImm(SDValue N, SDValue &Op) {
2654+
if (auto *CN = dyn_cast<ConstantSDNode>(N)) {
2655+
Op = CurDAG->getTargetConstant(CN->getAPIntValue(), SDLoc(CN),
2656+
N.getValueType());
2657+
return true;
2658+
}
2659+
26462660
// Keep track of the original value type and whether this value was
26472661
// truncated. If we see a truncation from pointer type to VT that truncates
26482662
// bits that are known to be zero, we can use a narrow reference.

‎llvm/lib/Target/X86/X86InstrArithmetic.td‎

Lines changed: 4 additions & 163 deletions
Original file line numberDiff line numberDiff line change
@@ -605,16 +605,16 @@ def invalid_node : SDNode<"<<invalid_node>>", SDTIntLeaf,[],"<<invalid_node>>">;
605605

606606

607607
def Xi8 : X86TypeInfo<i8, "b", GR8, loadi8, i8mem,
608-
Imm8, i8imm, imm_su, i8imm, invalid_node,
608+
Imm8, i8imm, relocImm8_su, i8imm, invalid_node,
609609
0, OpSizeFixed, 0>;
610610
def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem,
611-
Imm16, i16imm, imm_su, i16i8imm, i16immSExt8_su,
611+
Imm16, i16imm, relocImm16_su, i16i8imm, i16immSExt8_su,
612612
1, OpSize16, 0>;
613613
def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem,
614-
Imm32, i32imm, imm_su, i32i8imm, i32immSExt8_su,
614+
Imm32, i32imm, relocImm32_su, i32i8imm, i32immSExt8_su,
615615
1, OpSize32, 0>;
616616
def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem,
617-
Imm32S, i64i32imm, i64immSExt32_su, i64i8imm, i64immSExt8_su,
617+
Imm32S, i64i32imm, i64relocImmSExt32_su, i64i8imm, i64immSExt8_su,
618618
1, OpSizeFixed, 1>;
619619

620620
/// ITy - This instruction base class takes the type info for the instruction.
@@ -1217,146 +1217,6 @@ def : Pat<(store (X86adc_flag GR64:$src, (loadi64 addr:$dst), EFLAGS),
12171217
addr:$dst),
12181218
(ADC64mr addr:$dst, GR64:$src)>;
12191219

1220-
// Patterns for basic arithmetic ops with relocImm for the immediate field.
1221-
multiclass ArithBinOp_RF_relocImm_Pats<SDNode OpNodeFlag, SDNode OpNode> {
1222-
def : Pat<(OpNodeFlag GR8:$src1, relocImm8_su:$src2),
1223-
(!cast<Instruction>(NAME#"8ri") GR8:$src1, relocImm8_su:$src2)>;
1224-
def : Pat<(OpNodeFlag GR16:$src1, i16relocImmSExt8_su:$src2),
1225-
(!cast<Instruction>(NAME#"16ri8") GR16:$src1, i16relocImmSExt8_su:$src2)>;
1226-
def : Pat<(OpNodeFlag GR16:$src1, relocImm16_su:$src2),
1227-
(!cast<Instruction>(NAME#"16ri") GR16:$src1, relocImm16_su:$src2)>;
1228-
def : Pat<(OpNodeFlag GR32:$src1, i32relocImmSExt8_su:$src2),
1229-
(!cast<Instruction>(NAME#"32ri8") GR32:$src1, i32relocImmSExt8_su:$src2)>;
1230-
def : Pat<(OpNodeFlag GR32:$src1, relocImm32_su:$src2),
1231-
(!cast<Instruction>(NAME#"32ri") GR32:$src1, relocImm32_su:$src2)>;
1232-
def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt8_su:$src2),
1233-
(!cast<Instruction>(NAME#"64ri8") GR64:$src1, i64relocImmSExt8_su:$src2)>;
1234-
def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt32_su:$src2),
1235-
(!cast<Instruction>(NAME#"64ri32") GR64:$src1, i64relocImmSExt32_su:$src2)>;
1236-
1237-
def : Pat<(store (OpNode (load addr:$dst), relocImm8_su:$src), addr:$dst),
1238-
(!cast<Instruction>(NAME#"8mi") addr:$dst, relocImm8_su:$src)>;
1239-
def : Pat<(store (OpNode (load addr:$dst), i16relocImmSExt8_su:$src), addr:$dst),
1240-
(!cast<Instruction>(NAME#"16mi8") addr:$dst, i16relocImmSExt8_su:$src)>;
1241-
def : Pat<(store (OpNode (load addr:$dst), relocImm16_su:$src), addr:$dst),
1242-
(!cast<Instruction>(NAME#"16mi") addr:$dst, relocImm16_su:$src)>;
1243-
def : Pat<(store (OpNode (load addr:$dst), i32relocImmSExt8_su:$src), addr:$dst),
1244-
(!cast<Instruction>(NAME#"32mi8") addr:$dst, i32relocImmSExt8_su:$src)>;
1245-
def : Pat<(store (OpNode (load addr:$dst), relocImm32_su:$src), addr:$dst),
1246-
(!cast<Instruction>(NAME#"32mi") addr:$dst, relocImm32_su:$src)>;
1247-
def : Pat<(store (OpNode (load addr:$dst), i64relocImmSExt8_su:$src), addr:$dst),
1248-
(!cast<Instruction>(NAME#"64mi8") addr:$dst, i64relocImmSExt8_su:$src)>;
1249-
def : Pat<(store (OpNode (load addr:$dst), i64relocImmSExt32_su:$src), addr:$dst),
1250-
(!cast<Instruction>(NAME#"64mi32") addr:$dst, i64relocImmSExt32_su:$src)>;
1251-
}
1252-
1253-
multiclass ArithBinOp_RFF_relocImm_Pats<SDNode OpNodeFlag> {
1254-
def : Pat<(OpNodeFlag GR8:$src1, relocImm8_su:$src2, EFLAGS),
1255-
(!cast<Instruction>(NAME#"8ri") GR8:$src1, relocImm8_su:$src2)>;
1256-
def : Pat<(OpNodeFlag GR16:$src1, i16relocImmSExt8_su:$src2, EFLAGS),
1257-
(!cast<Instruction>(NAME#"16ri8") GR16:$src1, i16relocImmSExt8_su:$src2)>;
1258-
def : Pat<(OpNodeFlag GR16:$src1, relocImm16_su:$src2, EFLAGS),
1259-
(!cast<Instruction>(NAME#"16ri") GR16:$src1, relocImm16_su:$src2)>;
1260-
def : Pat<(OpNodeFlag GR32:$src1, i32relocImmSExt8_su:$src2, EFLAGS),
1261-
(!cast<Instruction>(NAME#"32ri8") GR32:$src1, i32relocImmSExt8_su:$src2)>;
1262-
def : Pat<(OpNodeFlag GR32:$src1, relocImm32_su:$src2, EFLAGS),
1263-
(!cast<Instruction>(NAME#"32ri") GR32:$src1, relocImm32_su:$src2)>;
1264-
def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt8_su:$src2, EFLAGS),
1265-
(!cast<Instruction>(NAME#"64ri8") GR64:$src1, i64relocImmSExt8_su:$src2)>;
1266-
def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt32_su:$src2, EFLAGS),
1267-
(!cast<Instruction>(NAME#"64ri32") GR64:$src1, i64relocImmSExt32_su:$src2)>;
1268-
1269-
def : Pat<(store (OpNodeFlag (load addr:$dst), relocImm8_su:$src, EFLAGS), addr:$dst),
1270-
(!cast<Instruction>(NAME#"8mi") addr:$dst, relocImm8_su:$src)>;
1271-
def : Pat<(store (OpNodeFlag (load addr:$dst), i16relocImmSExt8_su:$src, EFLAGS), addr:$dst),
1272-
(!cast<Instruction>(NAME#"16mi8") addr:$dst, i16relocImmSExt8_su:$src)>;
1273-
def : Pat<(store (OpNodeFlag (load addr:$dst), relocImm16_su:$src, EFLAGS), addr:$dst),
1274-
(!cast<Instruction>(NAME#"16mi") addr:$dst, relocImm16_su:$src)>;
1275-
def : Pat<(store (OpNodeFlag (load addr:$dst), i32relocImmSExt8_su:$src, EFLAGS), addr:$dst),
1276-
(!cast<Instruction>(NAME#"32mi8") addr:$dst, i32relocImmSExt8_su:$src)>;
1277-
def : Pat<(store (OpNodeFlag (load addr:$dst), relocImm32_su:$src, EFLAGS), addr:$dst),
1278-
(!cast<Instruction>(NAME#"32mi") addr:$dst, relocImm32_su:$src)>;
1279-
def : Pat<(store (OpNodeFlag (load addr:$dst), i64relocImmSExt8_su:$src, EFLAGS), addr:$dst),
1280-
(!cast<Instruction>(NAME#"64mi8") addr:$dst, i64relocImmSExt8_su:$src)>;
1281-
def : Pat<(store (OpNodeFlag (load addr:$dst), i64relocImmSExt32_su:$src, EFLAGS), addr:$dst),
1282-
(!cast<Instruction>(NAME#"64mi32") addr:$dst, i64relocImmSExt32_su:$src)>;
1283-
}
1284-
1285-
multiclass ArithBinOp_F_relocImm_Pats<SDNode OpNodeFlag> {
1286-
def : Pat<(OpNodeFlag GR8:$src1, relocImm8_su:$src2),
1287-
(!cast<Instruction>(NAME#"8ri") GR8:$src1, relocImm8_su:$src2)>;
1288-
def : Pat<(OpNodeFlag GR16:$src1, i16relocImmSExt8_su:$src2),
1289-
(!cast<Instruction>(NAME#"16ri8") GR16:$src1, i16relocImmSExt8_su:$src2)>;
1290-
def : Pat<(OpNodeFlag GR16:$src1, relocImm16_su:$src2),
1291-
(!cast<Instruction>(NAME#"16ri") GR16:$src1, relocImm16_su:$src2)>;
1292-
def : Pat<(OpNodeFlag GR32:$src1, i32relocImmSExt8_su:$src2),
1293-
(!cast<Instruction>(NAME#"32ri8") GR32:$src1, i32relocImmSExt8_su:$src2)>;
1294-
def : Pat<(OpNodeFlag GR32:$src1, relocImm32_su:$src2),
1295-
(!cast<Instruction>(NAME#"32ri") GR32:$src1, relocImm32_su:$src2)>;
1296-
def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt8_su:$src2),
1297-
(!cast<Instruction>(NAME#"64ri8") GR64:$src1, i64relocImmSExt8_su:$src2)>;
1298-
def : Pat<(OpNodeFlag GR64:$src1, i64relocImmSExt32_su:$src2),
1299-
(!cast<Instruction>(NAME#"64ri32") GR64:$src1, i64relocImmSExt32_su:$src2)>;
1300-
1301-
def : Pat<(OpNodeFlag (loadi8 addr:$src1), relocImm8_su:$src2),
1302-
(!cast<Instruction>(NAME#"8mi") addr:$src1, relocImm8_su:$src2)>;
1303-
def : Pat<(OpNodeFlag (loadi16 addr:$src1), i16relocImmSExt8_su:$src2),
1304-
(!cast<Instruction>(NAME#"16mi8") addr:$src1, i16relocImmSExt8_su:$src2)>;
1305-
def : Pat<(OpNodeFlag (loadi16 addr:$src1), relocImm16_su:$src2),
1306-
(!cast<Instruction>(NAME#"16mi") addr:$src1, relocImm16_su:$src2)>;
1307-
def : Pat<(OpNodeFlag (loadi32 addr:$src1), i32relocImmSExt8_su:$src2),
1308-
(!cast<Instruction>(NAME#"32mi8") addr:$src1, i32relocImmSExt8_su:$src2)>;
1309-
def : Pat<(OpNodeFlag (loadi32 addr:$src1), relocImm32_su:$src2),
1310-
(!cast<Instruction>(NAME#"32mi") addr:$src1, relocImm32_su:$src2)>;
1311-
def : Pat<(OpNodeFlag (loadi64 addr:$src1), i64relocImmSExt8_su:$src2),
1312-
(!cast<Instruction>(NAME#"64mi8") addr:$src1, i64relocImmSExt8_su:$src2)>;
1313-
def : Pat<(OpNodeFlag (loadi64 addr:$src1), i64relocImmSExt32_su:$src2),
1314-
(!cast<Instruction>(NAME#"64mi32") addr:$src1, i64relocImmSExt32_su:$src2)>;
1315-
}
1316-
1317-
defm AND : ArithBinOp_RF_relocImm_Pats<X86and_flag, and>;
1318-
defm OR : ArithBinOp_RF_relocImm_Pats<X86or_flag, or>;
1319-
defm XOR : ArithBinOp_RF_relocImm_Pats<X86xor_flag, xor>;
1320-
defm ADD : ArithBinOp_RF_relocImm_Pats<X86add_flag, add>;
1321-
defm SUB : ArithBinOp_RF_relocImm_Pats<X86sub_flag, sub>;
1322-
1323-
defm ADC : ArithBinOp_RFF_relocImm_Pats<X86adc_flag>;
1324-
defm SBB : ArithBinOp_RFF_relocImm_Pats<X86sbb_flag>;
1325-
1326-
defm CMP : ArithBinOp_F_relocImm_Pats<X86cmp>;
1327-
1328-
// ADC is commutable, but we can't indicate that to tablegen. So manually
1329-
// reverse the operands.
1330-
def : Pat<(X86adc_flag GR8:$src1, relocImm8_su:$src2, EFLAGS),
1331-
(ADC8ri relocImm8_su:$src2, GR8:$src1)>;
1332-
def : Pat<(X86adc_flag i16relocImmSExt8_su:$src2, GR16:$src1, EFLAGS),
1333-
(ADC16ri8 GR16:$src1, i16relocImmSExt8_su:$src2)>;
1334-
def : Pat<(X86adc_flag relocImm16_su:$src2, GR16:$src1, EFLAGS),
1335-
(ADC16ri GR16:$src1, relocImm16_su:$src2)>;
1336-
def : Pat<(X86adc_flag i32relocImmSExt8_su:$src2, GR32:$src1, EFLAGS),
1337-
(ADC32ri8 GR32:$src1, i32relocImmSExt8_su:$src2)>;
1338-
def : Pat<(X86adc_flag relocImm32_su:$src2, GR32:$src1, EFLAGS),
1339-
(ADC32ri GR32:$src1, relocImm32_su:$src2)>;
1340-
def : Pat<(X86adc_flag i64relocImmSExt8_su:$src2, GR64:$src1, EFLAGS),
1341-
(ADC64ri8 GR64:$src1, i64relocImmSExt8_su:$src2)>;
1342-
def : Pat<(X86adc_flag i64relocImmSExt32_su:$src2, GR64:$src1, EFLAGS),
1343-
(ADC64ri32 GR64:$src1, i64relocImmSExt32_su:$src2)>;
1344-
1345-
def : Pat<(store (X86adc_flag relocImm8_su:$src, (load addr:$dst), EFLAGS), addr:$dst),
1346-
(ADC8mi addr:$dst, relocImm8_su:$src)>;
1347-
def : Pat<(store (X86adc_flag i16relocImmSExt8_su:$src, (load addr:$dst), EFLAGS), addr:$dst),
1348-
(ADC16mi8 addr:$dst, i16relocImmSExt8_su:$src)>;
1349-
def : Pat<(store (X86adc_flag relocImm16_su:$src, (load addr:$dst), EFLAGS), addr:$dst),
1350-
(ADC16mi addr:$dst, relocImm16_su:$src)>;
1351-
def : Pat<(store (X86adc_flag i32relocImmSExt8_su:$src, (load addr:$dst), EFLAGS), addr:$dst),
1352-
(ADC32mi8 addr:$dst, i32relocImmSExt8_su:$src)>;
1353-
def : Pat<(store (X86adc_flag relocImm32_su:$src, (load addr:$dst), EFLAGS), addr:$dst),
1354-
(ADC32mi addr:$dst, relocImm32_su:$src)>;
1355-
def : Pat<(store (X86adc_flag i64relocImmSExt8_su:$src, (load addr:$dst), EFLAGS), addr:$dst),
1356-
(ADC64mi8 addr:$dst, i64relocImmSExt8_su:$src)>;
1357-
def : Pat<(store (X86adc_flag i64relocImmSExt32_su:$src, (load addr:$dst), EFLAGS), addr:$dst),
1358-
(ADC64mi32 addr:$dst, i64relocImmSExt32_su:$src)>;
1359-
13601220
//===----------------------------------------------------------------------===//
13611221
// Semantically, test instructions are similar like AND, except they don't
13621222
// generate a result. From an encoding perspective, they are very different:
@@ -1406,25 +1266,6 @@ let isCompare = 1 in {
14061266
"{$src, %rax|rax, $src}">;
14071267
} // isCompare
14081268

1409-
// Patterns to match a relocImm into the immediate field.
1410-
def : Pat<(X86testpat GR8:$src1, relocImm8_su:$src2),
1411-
(TEST8ri addr:$src1, relocImm8_su:$src2)>;
1412-
def : Pat<(X86testpat GR16:$src1, relocImm16_su:$src2),
1413-
(TEST16ri GR16:$src1, relocImm16_su:$src2)>;
1414-
def : Pat<(X86testpat GR32:$src1, relocImm32_su:$src2),
1415-
(TEST32ri GR32:$src1, relocImm32_su:$src2)>;
1416-
def : Pat<(X86testpat GR64:$src1, i64relocImmSExt32_su:$src2),
1417-
(TEST64ri32 GR64:$src1, i64relocImmSExt32_su:$src2)>;
1418-
1419-
def : Pat<(X86testpat (loadi8 addr:$src1), relocImm8_su:$src2),
1420-
(TEST8mi addr:$src1, relocImm8_su:$src2)>;
1421-
def : Pat<(X86testpat (loadi16 addr:$src1), relocImm16_su:$src2),
1422-
(TEST16mi addr:$src1, relocImm16_su:$src2)>;
1423-
def : Pat<(X86testpat (loadi32 addr:$src1), relocImm32_su:$src2),
1424-
(TEST32mi addr:$src1, relocImm32_su:$src2)>;
1425-
def : Pat<(X86testpat (loadi64 addr:$src1), i64relocImmSExt32_su:$src2),
1426-
(TEST64mi32 addr:$src1, i64relocImmSExt32_su:$src2)>;
1427-
14281269
//===----------------------------------------------------------------------===//
14291270
// ANDN Instruction
14301271
//

‎llvm/lib/Target/X86/X86InstrCompiler.td‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1964,6 +1964,10 @@ def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
19641964
def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
19651965
def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
19661966

1967+
// sub reg, relocImm
1968+
def : Pat<(X86sub_flag GR64:$src1, i64relocImmSExt8_su:$src2),
1969+
(SUB64ri8 GR64:$src1, i64relocImmSExt8_su:$src2)>;
1970+
19671971
// mul reg, reg
19681972
def : Pat<(mul GR16:$src1, GR16:$src2),
19691973
(IMUL16rr GR16:$src1, GR16:$src2)>;

‎llvm/lib/Target/X86/X86InstrInfo.td‎

Lines changed: 20 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -837,10 +837,11 @@ def tls64baseaddr : ComplexPattern<i64, 5, "selectTLSADDRAddr",
837837

838838
def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>;
839839

840-
// A relocatable immediate is an operand that can be relocated by the linker to
841-
// an immediate, such as a regular symbol in non-PIC code.
842-
def relocImm : ComplexPattern<iAny, 1, "selectRelocImm",
843-
[X86Wrapper], [], 0>;
840+
// A relocatable immediate is either an immediate operand or an operand that can
841+
// be relocated by the linker to an immediate, such as a regular symbol in
842+
// non-PIC code.
843+
def relocImm : ComplexPattern<iAny, 1, "selectRelocImm", [imm, X86Wrapper], [],
844+
0>;
844845

845846
//===----------------------------------------------------------------------===//
846847
// X86 Instruction Predicate Definitions.
@@ -1041,17 +1042,13 @@ def i32immSExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>;
10411042
def i64immSExt8 : ImmLeaf<i64, [{ return isInt<8>(Imm); }]>;
10421043
def i64immSExt32 : ImmLeaf<i64, [{ return isInt<32>(Imm); }]>;
10431044

1044-
def i16relocImmSExt8 : PatLeaf<(i16 relocImm), [{
1045-
return isSExtAbsoluteSymbolRef(8, N);
1046-
}]>;
1047-
def i32relocImmSExt8 : PatLeaf<(i32 relocImm), [{
1048-
return isSExtAbsoluteSymbolRef(8, N);
1049-
}]>;
1045+
// FIXME: Ideally we would just replace the above i*immSExt* matchers with
1046+
// relocImm-based matchers, but then FastISel would be unable to use them.
10501047
def i64relocImmSExt8 : PatLeaf<(i64 relocImm), [{
1051-
return isSExtAbsoluteSymbolRef(8, N);
1048+
return isSExtRelocImm<8>(N);
10521049
}]>;
10531050
def i64relocImmSExt32 : PatLeaf<(i64 relocImm), [{
1054-
return isSExtAbsoluteSymbolRef(32, N);
1051+
return isSExtRelocImm<32>(N);
10551052
}]>;
10561053

10571054
// If we have multiple users of an immediate, it's much smaller to reuse
@@ -1071,13 +1068,6 @@ def i64relocImmSExt32 : PatLeaf<(i64 relocImm), [{
10711068
// Eventually, it would be nice to allow ConstantHoisting to merge constants
10721069
// globally for potentially added savings.
10731070
//
1074-
def imm_su : PatLeaf<(imm), [{
1075-
return !shouldAvoidImmediateInstFormsForSize(N);
1076-
}]>;
1077-
def i64immSExt32_su : PatLeaf<(i64immSExt32), [{
1078-
return !shouldAvoidImmediateInstFormsForSize(N);
1079-
}]>;
1080-
10811071
def relocImm8_su : PatLeaf<(i8 relocImm), [{
10821072
return !shouldAvoidImmediateInstFormsForSize(N);
10831073
}]>;
@@ -1088,26 +1078,20 @@ def relocImm32_su : PatLeaf<(i32 relocImm), [{
10881078
return !shouldAvoidImmediateInstFormsForSize(N);
10891079
}]>;
10901080

1091-
def i16relocImmSExt8_su : PatLeaf<(i16relocImmSExt8), [{
1092-
return !shouldAvoidImmediateInstFormsForSize(N);
1093-
}]>;
1094-
def i32relocImmSExt8_su : PatLeaf<(i32relocImmSExt8), [{
1081+
def i16immSExt8_su : PatLeaf<(i16immSExt8), [{
10951082
return !shouldAvoidImmediateInstFormsForSize(N);
10961083
}]>;
1097-
def i64relocImmSExt8_su : PatLeaf<(i64relocImmSExt8), [{
1084+
def i32immSExt8_su : PatLeaf<(i32immSExt8), [{
10981085
return !shouldAvoidImmediateInstFormsForSize(N);
10991086
}]>;
1100-
def i64relocImmSExt32_su : PatLeaf<(i64relocImmSExt32), [{
1087+
def i64immSExt8_su : PatLeaf<(i64immSExt8), [{
11011088
return !shouldAvoidImmediateInstFormsForSize(N);
11021089
}]>;
11031090

1104-
def i16immSExt8_su : PatLeaf<(i16immSExt8), [{
1105-
return !shouldAvoidImmediateInstFormsForSize(N);
1106-
}]>;
1107-
def i32immSExt8_su : PatLeaf<(i32immSExt8), [{
1091+
def i64relocImmSExt8_su : PatLeaf<(i64relocImmSExt8), [{
11081092
return !shouldAvoidImmediateInstFormsForSize(N);
11091093
}]>;
1110-
def i64immSExt8_su : PatLeaf<(i64immSExt8), [{
1094+
def i64relocImmSExt32_su : PatLeaf<(i64relocImmSExt32), [{
11111095
return !shouldAvoidImmediateInstFormsForSize(N);
11121096
}]>;
11131097

@@ -1575,15 +1559,15 @@ def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
15751559
[(set GR16:$dst, imm:$src)]>, OpSize16;
15761560
def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
15771561
"mov{l}\t{$src, $dst|$dst, $src}",
1578-
[(set GR32:$dst, imm:$src)]>, OpSize32;
1562+
[(set GR32:$dst, relocImm:$src)]>, OpSize32;
15791563
def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
15801564
"mov{q}\t{$src, $dst|$dst, $src}",
15811565
[(set GR64:$dst, i64immSExt32:$src)]>;
15821566
}
15831567
let isReMaterializable = 1, isMoveImm = 1 in {
15841568
def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
15851569
"movabs{q}\t{$src, $dst|$dst, $src}",
1586-
[(set GR64:$dst, imm:$src)]>;
1570+
[(set GR64:$dst, relocImm:$src)]>;
15871571
}
15881572

15891573
// Longer forms that use a ModR/M byte. Needed for disassembler
@@ -1603,31 +1587,19 @@ def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
16031587
let SchedRW = [WriteStore] in {
16041588
def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
16051589
"mov{b}\t{$src, $dst|$dst, $src}",
1606-
[(store (i8 imm_su:$src), addr:$dst)]>;
1590+
[(store (i8 relocImm8_su:$src), addr:$dst)]>;
16071591
def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
16081592
"mov{w}\t{$src, $dst|$dst, $src}",
1609-
[(store (i16 imm_su:$src), addr:$dst)]>, OpSize16;
1593+
[(store (i16 relocImm16_su:$src), addr:$dst)]>, OpSize16;
16101594
def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
16111595
"mov{l}\t{$src, $dst|$dst, $src}",
1612-
[(store (i32 imm_su:$src), addr:$dst)]>, OpSize32;
1596+
[(store (i32 relocImm32_su:$src), addr:$dst)]>, OpSize32;
16131597
def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
16141598
"mov{q}\t{$src, $dst|$dst, $src}",
1615-
[(store i64immSExt32_su:$src, addr:$dst)]>,
1599+
[(store i64relocImmSExt32_su:$src, addr:$dst)]>,
16161600
Requires<[In64BitMode]>;
16171601
} // SchedRW
16181602

1619-
def : Pat<(i32 relocImm:$src), (MOV32ri relocImm:$src)>;
1620-
def : Pat<(i64 relocImm:$src), (MOV64ri relocImm:$src)>;
1621-
1622-
def : Pat<(store (i8 relocImm8_su:$src), addr:$dst),
1623-
(MOV8mi addr:$dst, relocImm8_su:$src)>;
1624-
def : Pat<(store (i16 relocImm16_su:$src), addr:$dst),
1625-
(MOV16mi addr:$dst, relocImm16_su:$src)>;
1626-
def : Pat<(store (i32 relocImm32_su:$src), addr:$dst),
1627-
(MOV32mi addr:$dst, relocImm32_su:$src)>;
1628-
def : Pat<(store (i64 i64relocImmSExt32_su:$src), addr:$dst),
1629-
(MOV64mi32 addr:$dst, i64immSExt32_su:$src)>;
1630-
16311603
let hasSideEffects = 0 in {
16321604

16331605
/// Memory offset versions of moves. The immediate is an address mode sized

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