[RISCV] Add SRAI to recursive part of isSignExtendedW.

[topperc]

SRAI can only increase the number of sign bits. If the input has at least 33 sign bits, the result will to.

I don't have a test case for this currently. It was just an observation I made while thinking about the shifts and extracts.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

Changes

SRAI can only increase the number of sign bits. If the input has at least 33 sign bits, the result will to.

I don't have a test case for this currently. It was just an observation I made while thinking about the shifts and extracts.

---

Full diff: https://github.com/llvm/llvm-project/pull/157164.diff

1 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp (+2)

diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index 3b19c3456ad67..e86c49dabfd64 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -519,9 +519,11 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
     case RISCV::ANDI:
     case RISCV::ORI:
     case RISCV::XORI:
+    case RISCV::SRAI:
       // |Remainder| is always <= |Dividend|. If D is 32-bit, then so is R.
       // DIV doesn't work because of the edge case 0xf..f 8000 0000 / (long)-1
       // Logical operations use a sign extended 12-bit immediate.
+      // Arithmetic shift right can only increase the number of sign bits.
       if (!AddRegToWorkList(MI->getOperand(1).getReg()))
         return false;
 

[preames]

LGTM