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[RISCV] Add SRAI to recursive part of isSignExtendedW. #157164

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Merged
merged 1 commit into from
Sep 5, 2025
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[RISCV] Add SRAI to recursive part of isSignExtendedW. #157164

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2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -519,9 +519,11 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
case RISCV::ANDI:
case RISCV::ORI:
case RISCV::XORI:
case RISCV::SRAI:
// |Remainder| is always <= |Dividend|. If D is 32-bit, then so is R.
// DIV doesn't work because of the edge case 0xf..f 8000 0000 / (long)-1
// Logical operations use a sign extended 12-bit immediate.
// Arithmetic shift right can only increase the number of sign bits.
if (!AddRegToWorkList(MI->getOperand(1).getReg()))
return false;

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